[MIPS] Cleanup memory barriers for weakly ordered systems.

[linux-2.6] / include / asm-mips / bitops.h

diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
index 8cd61c1970528c4225ec78881372235683c933f5..06445de1324bd3c058a507d08d0c747d6ab571ae 100644 (file)
--- a/include/asm-mips/bitops.h
+++ b/include/asm-mips/bitops.h
@@ -3,7 +3,7 @@
  * License.  See the file "COPYING" in the main directory of this archive
  * for more details.
  *
- * Copyright (c) 1994 - 1997, 1999, 2000  Ralf Baechle (ralf@gnu.org)
+ * Copyright (c) 1994 - 1997, 1999, 2000, 06  Ralf Baechle (ralf@linux-mips.org)
  * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
  */
 #ifndef _ASM_BITOPS_H
@@ -12,6 +12,7 @@
 #include <linux/compiler.h>
 #include <linux/irqflags.h>
 #include <linux/types.h>
+#include <asm/barrier.h>
 #include <asm/bug.h>
 #include <asm/byteorder.h>             /* sigh ... */
 #include <asm/cpu-features.h>
@@ -23,13 +24,11 @@
 #define SZLONG_MASK 31UL
 #define __LL           "ll     "
 #define __SC           "sc     "
-#define cpu_to_lelongp(x) cpu_to_le32p((__u32 *) (x))
 #elif (_MIPS_SZLONG == 64)
 #define SZLONG_LOG 6
 #define SZLONG_MASK 63UL
 #define __LL           "lld    "
 #define __SC           "scd    "
-#define cpu_to_lelongp(x) cpu_to_le64p((__u64 *) (x))
 #endif
 
 /*
@@ -206,9 +205,6 @@ static inline int test_and_set_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-               "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -228,9 +224,6 @@ static inline int test_and_set_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-               "       sync                                            \n"
-#endif
                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -252,6 +245,8 @@ static inline int test_and_set_bit(unsigned long nr,
 
                return retval;
        }
+
+       smp_mb();
 }
 
 /*
@@ -277,9 +272,6 @@ static inline int test_and_clear_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-               "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -300,9 +292,6 @@ static inline int test_and_clear_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-               "       sync                                            \n"
-#endif
                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -324,6 +313,8 @@ static inline int test_and_clear_bit(unsigned long nr,
 
                return retval;
        }
+
+       smp_mb();
 }
 
 /*
@@ -348,9 +339,6 @@ static inline int test_and_change_bit(unsigned long nr,
                "       " __SC  "%2, %1                                 \n"
                "       beqzl   %2, 1b                                  \n"
                "       and     %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-               "       sync                                            \n"
-#endif
                "       .set    mips0                                   \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -370,9 +358,6 @@ static inline int test_and_change_bit(unsigned long nr,
                "       " __SC  "\t%2, %1                               \n"
                "       beqz    %2, 1b                                  \n"
                "        and    %2, %0, %3                              \n"
-#ifdef CONFIG_SMP
-               "       sync                                            \n"
-#endif
                "       .set    pop                                     \n"
                : "=&r" (temp), "=m" (*m), "=&r" (res)
                : "r" (1UL << (nr & SZLONG_MASK)), "m" (*m)
@@ -393,6 +378,8 @@ static inline int test_and_change_bit(unsigned long nr,
 
                return retval;
        }
+
+       smp_mb();
 }
 
 #include <asm-generic/bitops/non-atomic.h>