* <linux/spinlock.h> we have to include <linux/spinlock.h> outside the
* main big wrapper ...
*/
-#include <linux/config.h>
#include <linux/spinlock.h>
#ifndef _ASM_ATOMIC_H
#define _ASM_ATOMIC_H
#include <asm/cpu-features.h>
+#include <asm/interrupt.h>
#include <asm/war.h>
-extern spinlock_t atomic_lock;
-
typedef struct { volatile int counter; } atomic_t;
#define ATOMIC_INIT(i) { (i) }
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
v->counter += i;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
}
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
v->counter -= i;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
}
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
result = v->counter;
result += i;
v->counter = result;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
return result;
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
result = v->counter;
result -= i;
v->counter = result;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
return result;
" subu %0, %1, %3 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
+ " .set noreorder \n"
" beqzl %0, 1b \n"
+ " subu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
" subu %0, %1, %3 \n"
" bltz %0, 1f \n"
" sc %0, %2 \n"
+ " .set noreorder \n"
" beqz %0, 1b \n"
+ " subu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
result = v->counter;
result -= i;
if (result >= 0)
v->counter = result;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
return result;
}
#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
/**
* atomic_add_unless - add unless the number is a given value
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
v->counter += i;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
}
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
v->counter -= i;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
}
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
result = v->counter;
result += i;
v->counter = result;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
return result;
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
result = v->counter;
result -= i;
v->counter = result;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
return result;
" dsubu %0, %1, %3 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
+ " .set noreorder \n"
" beqzl %0, 1b \n"
+ " dsubu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
" dsubu %0, %1, %3 \n"
" bltz %0, 1f \n"
" scd %0, %2 \n"
+ " .set noreorder \n"
" beqz %0, 1b \n"
+ " dsubu %0, %1, %3 \n"
+ " .set reorder \n"
" sync \n"
"1: \n"
" .set mips0 \n"
} else {
unsigned long flags;
- spin_lock_irqsave(&atomic_lock, flags);
+ local_irq_save(flags);
result = v->counter;
result -= i;
if (result >= 0)
v->counter = result;
- spin_unlock_irqrestore(&atomic_lock, flags);
+ local_irq_restore(flags);
}
return result;