Auto merge with /home/aegl/GIT/linus

[linux-2.6] / include / asm-ia64 / sn / addrs.h

diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h
index c916bd22767a14dae43f1405e3934dd1b77f7be6..103d745dc5f2f9fc8eda359854310424cd63545c 100644 (file)
--- a/include/asm-ia64/sn/addrs.h
+++ b/include/asm-ia64/sn/addrs.h
@@ -136,6 +136,7 @@
  */
 #define CAC_BASE               (CACHED   | AS_CAC_SPACE)
 #define AMO_BASE               (UNCACHED | AS_AMO_SPACE)
+#define AMO_PHYS_BASE          (UNCACHED_PHYS | AS_AMO_SPACE)
 #define GET_BASE               (CACHED   | AS_GET_SPACE)
 
 /*
@@ -154,11 +155,19 @@
  *           the chiplet id is zero.  If we implement TIO-TIO dma, we might need
  *           to insert a chiplet id into this macro.  However, it is our belief
  *           right now that this chiplet id will be ICE, which is also zero.
+ *           Nasid starts on bit 40.
  */
-#define PHYS_TO_TIODMA(x)      ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x))
+#define PHYS_TO_TIODMA(x)      ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x))
 #define PHYS_TO_DMA(x)          ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x))
 
 
+/*
+ * Macros to test for address type.
+ */
+#define IS_AMO_ADDRESS(x)      (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_BASE)
+#define IS_AMO_PHYS_ADDRESS(x) (((u64)(x) & (REGION_BITS | AS_MASK)) == AMO_PHYS_BASE)
+
+
 /*
  * The following definitions pertain to the IO special address
  * space.  They define the location of the big and little windows
@@ -168,7 +177,10 @@
 #define TIO_BWIN_SIZE_BITS             30      /* big window size: 1G */
 #define NODE_SWIN_BASE(n, w)           ((w == 0) ? NODE_BWIN_BASE((n), SWIN0_BIGWIN) \
                : RAW_NODE_SWIN_BASE(n, w))
+#define TIO_SWIN_BASE(n, w)            (TIO_IO_BASE(n) + \
+                                           ((u64) (w) << TIO_SWIN_SIZE_BITS))
 #define NODE_IO_BASE(n)                        (GLOBAL_MMR_SPACE | NASID_SPACE(n))
+#define TIO_IO_BASE(n)                  (UNCACHED | NASID_SPACE(n))
 #define BWIN_SIZE                      (1UL << BWIN_SIZE_BITS)
 #define NODE_BWIN_BASE0(n)             (NODE_IO_BASE(n) + BWIN_SIZE)
 #define NODE_BWIN_BASE(n, w)           (NODE_BWIN_BASE0(n) + ((u64) (w) << BWIN_SIZE_BITS))
@@ -204,6 +216,10 @@
 #define TIO_SWIN_WIDGETNUM(x)          (((x)  >> TIO_SWIN_SIZE_BITS) & TIO_SWIN_WIDGET_MASK)
 
 
+#define TIO_IOSPACE_ADDR(n,x)                                  \
+       /* Move in the Chiplet ID for TIO Local Block MMR */    \
+       (REMOTE_ADDR(n,x) | 1UL << (NASID_SHIFT - 2))
+
 /*
  * The following macros produce the correct base virtual address for
  * the hub registers. The REMOTE_HUB_* macro produce
@@ -221,13 +237,16 @@
 #define REMOTE_HUB_ADDR(n,x)                                           \
        ((n & 1) ?                                                      \
        /* TIO: */                                                      \
-       ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))                        \
-       : /* SHUB: */                                                   \
-       (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))\
+       (is_shub2() ?                                                   \
+       /* TIO on Shub2 */                                              \
+       (volatile u64 *)(TIO_IOSPACE_ADDR(n,x))                         \
+       : /* TIO on shub1 */                                            \
+       (volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))                         \
+                                                                       \
+       : /* SHUB1 and SHUB2 MMRs: */                                   \
+       (((x) & BWIN_TOP) ? ((volatile u64 *)(GLOBAL_MMR_ADDR(n,x)))    \
        : ((volatile u64 *)(NODE_SWIN_BASE(n,1) + 0x800000 + (x)))))
 
-
-
 #define HUB_L(x)                       (*((volatile typeof(*x) *)x))
 #define        HUB_S(x,d)                      (*((volatile typeof(*x) *)x) = (d))