[PATCH] do_notify_parent_cldstop() cleanup

[linux-2.6] / include / asm-ia64 / pal.h

diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 2303a10ee595405455d4f4520d3a334fd2fdfe56..e828377ad295cec5d77dd3a06b1bbdf06f014737 100644 (file)
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -75,6 +75,8 @@
 #define PAL_CACHE_READ         259     /* read tag & data of cacheline for diagnostic testing */
 #define PAL_CACHE_WRITE                260     /* write tag & data of cacheline for diagnostic testing */
 #define PAL_VM_TR_READ         261     /* read contents of translation register */
+#define PAL_GET_PSTATE         262     /* get the current P-state */
+#define PAL_SET_PSTATE         263     /* set the P-state */
 
 #ifndef __ASSEMBLY__
 
@@ -1111,6 +1113,25 @@ ia64_pal_halt_info (pal_power_mgmt_info_u_t *power_buf)
        return iprv.status;
 }
 
+/* Get the current P-state information */
+static inline s64
+ia64_pal_get_pstate (u64 *pstate_index)
+{
+       struct ia64_pal_retval iprv;
+       PAL_CALL_STK(iprv, PAL_GET_PSTATE, 0, 0, 0);
+       *pstate_index = iprv.v0;
+       return iprv.status;
+}
+
+/* Set the P-state */
+static inline s64
+ia64_pal_set_pstate (u64 pstate_index)
+{
+       struct ia64_pal_retval iprv;
+       PAL_CALL_STK(iprv, PAL_SET_PSTATE, pstate_index, 0, 0);
+       return iprv.status;
+}
+
 /* Cause the processor to enter LIGHT HALT state, where prefetching and execution are
  * suspended, but cache and TLB coherency is maintained.
  */