Merge branch 'release' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux...

[linux-2.6] / include / asm-blackfin / mach-bf561 / defBF561.h

diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 0f2dc6e6335b60b108eedbeeed11b8c6a7d495b7..c3c0eb13c819e43cd843bfdedb6bdbf039b57208 100644 (file)
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,10 @@
 /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
 #define SWRST                   SICA_SWRST
 #define SYSCR                   SICA_SYSCR
+#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
+#define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
+#define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
+#define RESET_SOFTWARE          (SWRST_OCCURRED)
 
 /* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
 #define SICA_SWRST              0xFFC00100     /* Software Reset register */
@@ -120,6 +124,7 @@
 #define UART_GCTL                      0xFFC00424      /* Global Control Register */
 
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI0_REGBASE                   0xFFC00500
 #define SPI_CTL                        0xFFC00500      /* SPI Control Register */
 #define SPI_FLG                        0xFFC00504      /* SPI Flag register */
 #define SPI_STAT                       0xFFC00508      /* SPI Status register */
@@ -873,12 +878,14 @@
 #define        PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* SWRST Mask */
-#define SYSTEM_RESET           0x00000007      /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_B      0x00000800      /* SWRST Core B Double Fault */
-#define SWRST_DBL_FAULT_A      0x00001000      /* SWRST Core A Double Fault */
-#define SWRST_WDT_B                   0x00002000       /* SWRST Watchdog B */
-#define SWRST_WDT_A                   0x00004000       /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x00008000      /* SWRST Status */
+#define SYSTEM_RESET           0x0007  /* Initiates a system software reset */
+#define DOUBLE_FAULT_A         0x0008  /* Core A Double Fault Causes Reset */
+#define DOUBLE_FAULT_B         0x0010  /* Core B Double Fault Causes Reset */
+#define SWRST_DBL_FAULT_A      0x0800  /* SWRST Core A Double Fault */
+#define SWRST_DBL_FAULT_B      0x1000  /* SWRST Core B Double Fault */
+#define SWRST_WDT_B                   0x2000   /* SWRST Watchdog B */
+#define SWRST_WDT_A                   0x4000   /* SWRST Watchdog A */
+#define SWRST_OCCURRED         0x8000  /* SWRST Status */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */