Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux...

[linux-2.6] / include / asm-blackfin / mach-bf561 / defBF561.h

diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
index 7945e8a3a8412fffa55c7b12ddd87773873e8bc4..366c9b9a0cb70cf2f345b2075024df35b8ea3671 100644 (file)
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -55,6 +55,7 @@
 /* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
 #define SWRST                   SICA_SWRST
 #define SYSCR                   SICA_SYSCR
+#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
 #define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
 #define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
 #define RESET_SOFTWARE          (SWRST_OCCURRED)
@@ -109,18 +110,23 @@
 #define WDOGB_STAT                             0xFFC01208      /* Watchdog Status register */
 
 /* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define UART_THR               0xFFC00400      /* Transmit Holding register */
-#define UART_RBR               0xFFC00400      /* Receive Buffer register */
-#define UART_DLL               0xFFC00400      /* Divisor Latch (Low-Byte) */
-#define UART_IER               0xFFC00404      /* Interrupt Enable Register */
-#define UART_DLH               0xFFC00404      /* Divisor Latch (High-Byte) */
-#define UART_IIR               0xFFC00408      /* Interrupt Identification Register */
-#define UART_LCR               0xFFC0040C      /* Line Control Register */
-#define UART_MCR                               0xFFC00410      /* Modem Control Register */
-#define UART_LSR               0xFFC00414      /* Line Status Register */
-#define UART_MSR               0xFFC00418      /* Modem Status Register */
-#define UART_SCR               0xFFC0041C      /* SCR Scratch Register */
-#define UART_GCTL                      0xFFC00424      /* Global Control Register */
+
+/*
+ * Because include/linux/serial_reg.h have defined UART_*,
+ * So we define blackfin uart regs to BFIN_UART0_*.
+ */
+#define BFIN_UART_THR                  0xFFC00400  /* Transmit Holding register */
+#define BFIN_UART_RBR                  0xFFC00400  /* Receive Buffer register */
+#define BFIN_UART_DLL                  0xFFC00400  /* Divisor Latch (Low-Byte) */
+#define BFIN_UART_IER                  0xFFC00404  /* Interrupt Enable Register */
+#define BFIN_UART_DLH                  0xFFC00404  /* Divisor Latch (High-Byte) */
+#define BFIN_UART_IIR                  0xFFC00408  /* Interrupt Identification Register */
+#define BFIN_UART_LCR                  0xFFC0040C  /* Line Control Register */
+#define BFIN_UART_MCR                  0xFFC00410  /* Modem Control Register */
+#define BFIN_UART_LSR                  0xFFC00414  /* Line Status Register */
+#define BFIN_UART_MSR                  0xFFC00418  /* Modem Status Register */
+#define BFIN_UART_SCR                  0xFFC0041C  /* SCR Scratch Register */
+#define BFIN_UART_GCTL                 0xFFC00424  /* Global Control Register */
 
 /* SPI Controller (0xFFC00500 - 0xFFC005FF) */
 #define SPI0_REGBASE                   0xFFC00500
@@ -865,6 +871,8 @@
 /* PLL_DIV Masks */
 #define SCLK_DIV(x)  (x)       /* SCLK = VCO / x */
 
+#define CSEL                   0x30            /* Core Select */
+#define SSEL                   0xf             /* System Select */
 #define CCLK_DIV1              0x00000000      /* CCLK = VCO / 1 */
 #define CCLK_DIV2              0x00000010      /* CCLK = VCO / 2 */
 #define CCLK_DIV4              0x00000020      /* CCLK = VCO / 4 */
@@ -877,12 +885,14 @@
 #define        PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
 
 /* SWRST Mask */
-#define SYSTEM_RESET           0x00000007      /* Initiates a system software reset */
-#define SWRST_DBL_FAULT_B      0x00000800      /* SWRST Core B Double Fault */
-#define SWRST_DBL_FAULT_A      0x00001000      /* SWRST Core A Double Fault */
-#define SWRST_WDT_B                   0x00002000       /* SWRST Watchdog B */
-#define SWRST_WDT_A                   0x00004000       /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x00008000      /* SWRST Status */
+#define SYSTEM_RESET           0x0007  /* Initiates a system software reset */
+#define DOUBLE_FAULT_A         0x0008  /* Core A Double Fault Causes Reset */
+#define DOUBLE_FAULT_B         0x0010  /* Core B Double Fault Causes Reset */
+#define SWRST_DBL_FAULT_A      0x0800  /* SWRST Core A Double Fault */
+#define SWRST_DBL_FAULT_B      0x1000  /* SWRST Core B Double Fault */
+#define SWRST_WDT_B                   0x2000   /* SWRST Watchdog B */
+#define SWRST_WDT_A                   0x4000   /* SWRST Watchdog A */
+#define SWRST_OCCURRED         0x8000  /* SWRST Status */
 
 /* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */