#ifndef _CDEF_BF561_H
#define _CDEF_BF561_H
-/*
-#if !defined(__ADSPBF561__)
-#warning cdefBF561.h should only be included for BF561 chip.
-#endif
-*/
+#include <asm/blackfin.h>
+
/* include all Core registers and bit definitions */
#include "defBF561.h"
/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL,val)
+/* Writing to PLL_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_PLL_CTL(unsigned int val)
+{
+ unsigned long flags, iwr0, iwr1;
+
+ if (val == bfin_read_PLL_CTL())
+ return;
+
+ local_irq_save(flags);
+ /* Enable the PLL Wakeup bit in SIC IWR */
+ iwr0 = bfin_read32(SICA_IWR0);
+ iwr1 = bfin_read32(SICA_IWR1);
+ /* Only allow PPL Wakeup) */
+ bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+ bfin_write32(SICA_IWR1, 0);
+
+ bfin_write16(PLL_CTL, val);
+ SSYNC();
+ asm("IDLE;");
+
+ bfin_write32(SICA_IWR0, iwr0);
+ bfin_write32(SICA_IWR1, iwr1);
+ local_irq_restore(flags);
+}
#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV,val)
#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
{
unsigned long flags, iwr0, iwr1;
+ if (val == bfin_read_VR_CTL())
+ return;
+
+ local_irq_save(flags);
/* Enable the PLL Wakeup bit in SIC IWR */
iwr0 = bfin_read32(SICA_IWR0);
iwr1 = bfin_read32(SICA_IWR1);
bfin_write32(SICA_IWR1, 0);
bfin_write16(VR_CTL, val);
- __builtin_bfin_ssync();
-
- local_irq_save(flags);
+ SSYNC();
asm("IDLE;");
- local_irq_restore(flags);
+
bfin_write32(SICA_IWR0, iwr0);
bfin_write32(SICA_IWR1, iwr1);
+ local_irq_restore(flags);
}
#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT,val)
/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
#define bfin_read_SWRST() bfin_read_SICA_SWRST()
-#define bfin_write_SWRST() bfin_write_SICA_SWRST()
+#define bfin_write_SWRST(val) bfin_write_SICA_SWRST(val)
#define bfin_read_SYSCR() bfin_read_SICA_SYSCR()
-#define bfin_write_SYSCR() bfin_write_SICA_SYSCR()
+#define bfin_write_SYSCR(val) bfin_write_SICA_SYSCR(val)
/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
#define bfin_read_SICA_SWRST() bfin_read16(SICA_SWRST)
#define bfin_write_PPI0_CONTROL(val) bfin_write16(PPI0_CONTROL,val)
#define bfin_read_PPI0_STATUS() bfin_read16(PPI0_STATUS)
#define bfin_write_PPI0_STATUS(val) bfin_write16(PPI0_STATUS,val)
+#define bfin_clear_PPI0_STATUS() bfin_read_PPI0_STATUS()
#define bfin_read_PPI0_COUNT() bfin_read16(PPI0_COUNT)
#define bfin_write_PPI0_COUNT(val) bfin_write16(PPI0_COUNT,val)
#define bfin_read_PPI0_DELAY() bfin_read16(PPI0_DELAY)
#define bfin_write_PPI1_CONTROL(val) bfin_write16(PPI1_CONTROL,val)
#define bfin_read_PPI1_STATUS() bfin_read16(PPI1_STATUS)
#define bfin_write_PPI1_STATUS(val) bfin_write16(PPI1_STATUS,val)
+#define bfin_clear_PPI1_STATUS() bfin_read_PPI1_STATUS()
#define bfin_read_PPI1_COUNT() bfin_read16(PPI1_COUNT)
#define bfin_write_PPI1_COUNT(val) bfin_write16(PPI1_COUNT,val)
#define bfin_read_PPI1_DELAY() bfin_read16(PPI1_DELAY)