+/*
+ * file: include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ * blackfin serial driver head file
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs: enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose. see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
#include <linux/serial.h>
#include <asm/dma.h>
-
-#define NR_PORTS 1
-
-#define OFFSET_THR 0x00 /* Transmit Holding register */
-#define OFFSET_RBR 0x00 /* Receive Buffer register */
-#define OFFSET_DLL 0x00 /* Divisor Latch (Low-Byte) */
-#define OFFSET_IER 0x04 /* Interrupt Enable Register */
-#define OFFSET_DLH 0x04 /* Divisor Latch (High-Byte) */
-#define OFFSET_IIR 0x08 /* Interrupt Identification Register */
-#define OFFSET_LCR 0x0C /* Line Control Register */
-#define OFFSET_MCR 0x10 /* Modem Control Register */
-#define OFFSET_LSR 0x14 /* Line Status Register */
-#define OFFSET_MSR 0x18 /* Modem Status Register */
-#define OFFSET_SCR 0x1C /* SCR Scratch Register */
-#define OFFSET_GCTL 0x24 /* Global Control Register */
+#include <asm/portmux.h>
#define UART_GET_CHAR(uart) bfin_read16(((uart)->port.membase + OFFSET_RBR))
#define UART_GET_DLL(uart) bfin_read16(((uart)->port.membase + OFFSET_DLL))
#define UART_GET_DLH(uart) bfin_read16(((uart)->port.membase + OFFSET_DLH))
#define UART_GET_IIR(uart) bfin_read16(((uart)->port.membase + OFFSET_IIR))
#define UART_GET_LCR(uart) bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_LSR(uart) bfin_read16(((uart)->port.membase + OFFSET_LSR))
#define UART_GET_GCTL(uart) bfin_read16(((uart)->port.membase + OFFSET_GCTL))
#define UART_PUT_CHAR(uart,v) bfin_write16(((uart)->port.membase + OFFSET_THR),v)
struct bfin_serial_port {
struct uart_port port;
unsigned int old_status;
+ unsigned int lsr;
#ifdef CONFIG_SERIAL_BFIN_DMA
int tx_done;
int tx_count;
unsigned int rx_dma_channel;
struct work_struct tx_dma_workqueue;
#else
- struct work_struct cts_workqueue;
+# if ANOMALY_05000230
+ unsigned int anomaly_threshold;
+# endif
#endif
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+ struct work_struct cts_workqueue;
int cts_pin;
int rts_pin;
#endif
};
-struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+/* The hardware clears the LSR bits upon read, so we need to cache
+ * some of the more fun bits in software so they don't get lost
+ * when checking the LSR in other code paths (TX).
+ */
+static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
+{
+ unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
+ uart->lsr |= (lsr & (BI|FE|PE|OE));
+ return lsr | uart->lsr;
+}
+
+static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
+{
+ uart->lsr = 0;
+ bfin_write16(uart->port.membase + OFFSET_LSR, -1);
+}
+
+struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
struct bfin_serial_res {
unsigned long uart_base_addr;
int uart_irq;
}
};
+#define DRIVER_NAME "bfin-uart"
-int nr_ports = NR_PORTS;
+int nr_ports = BFIN_UART_NR_PORTS;
static void bfin_serial_hw_init(struct bfin_serial_port *uart)
{
+#ifdef CONFIG_SERIAL_BFIN_UART0
+ peripheral_request(P_UART0_TX, DRIVER_NAME);
+ peripheral_request(P_UART0_RX, DRIVER_NAME);
+#endif
+
#ifdef CONFIG_SERIAL_BFIN_CTSRTS
if (uart->cts_pin >= 0) {
- gpio_request(uart->cts_pin, NULL);
+ gpio_request(uart->cts_pin, DRIVER_NAME);
gpio_direction_input(uart->cts_pin);
}
if (uart->rts_pin >= 0) {
- gpio_request(uart->rts_pin, NULL);
- gpio_direction_input(uart->rts_pin);
+ gpio_request(uart->rts_pin, DRIVER_NAME);
+ gpio_direction_input(uart->rts_pin, 0);
}
#endif
}