Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6

[linux-2.6] / include / asm-avr32 / io.h

diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h
index 2fc8f111dce9e43ca010ca8c474986c4feb78295..c08e810483936534ba6da061cde31a6050dfb904 100644 (file)
--- a/include/asm-avr32/io.h
+++ b/include/asm-avr32/io.h
@@ -28,13 +28,13 @@ static __inline__ void * phys_to_virt(unsigned long address)
  * Generic IO read/write.  These perform native-endian accesses.  Note
  * that some architectures will want to re-define __raw_{read,write}w.
  */
-extern void __raw_writesb(unsigned int addr, const void *data, int bytelen);
-extern void __raw_writesw(unsigned int addr, const void *data, int wordlen);
-extern void __raw_writesl(unsigned int addr, const void *data, int longlen);
+extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
+extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
+extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
 
-extern void __raw_readsb(unsigned int addr, void *data, int bytelen);
-extern void __raw_readsw(unsigned int addr, void *data, int wordlen);
-extern void __raw_readsl(unsigned int addr, void *data, int longlen);
+extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
+extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
+extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 
 static inline void writeb(unsigned char b, volatile void __iomem *addr)
 {
@@ -76,6 +76,39 @@ static inline unsigned int readl(const volatile void __iomem *addr)
 #define readsw(p, d, l)                __raw_readsw((unsigned int)p, d, l)
 #define readsl(p, d, l)                __raw_readsl((unsigned int)p, d, l)
 
+
+/*
+ * io{read,write}{8,16,32} macros in both le (for PCI style consumers) and native be
+ */
+#ifndef ioread8
+
+#define ioread8(p)     ({ unsigned int __v = __raw_readb(p); __v; })
+
+#define ioread16(p)    ({ unsigned int __v = le16_to_cpu(__raw_readw(p)); __v; })
+#define ioread16be(p)  ({ unsigned int __v = be16_to_cpu(__raw_readw(p)); __v; })
+
+#define ioread32(p)    ({ unsigned int __v = le32_to_cpu(__raw_readl(p)); __v; })
+#define ioread32be(p)  ({ unsigned int __v = be32_to_cpu(__raw_readl(p)); __v; })
+
+#define iowrite8(v,p)  __raw_writeb(v, p)
+
+#define iowrite16(v,p) __raw_writew(cpu_to_le16(v), p)
+#define iowrite16be(v,p)       __raw_writew(cpu_to_be16(v), p)
+
+#define iowrite32(v,p) __raw_writel(cpu_to_le32(v), p)
+#define iowrite32be(v,p)       __raw_writel(cpu_to_be32(v), p)
+
+#define ioread8_rep(p,d,c)     __raw_readsb(p,d,c)
+#define ioread16_rep(p,d,c)    __raw_readsw(p,d,c)
+#define ioread32_rep(p,d,c)    __raw_readsl(p,d,c)
+
+#define iowrite8_rep(p,s,c)    __raw_writesb(p,s,c)
+#define iowrite16_rep(p,s,c)   __raw_writesw(p,s,c)
+#define iowrite32_rep(p,s,c)   __raw_writesl(p,s,c)
+
+#endif
+
+
 /*
  * These two are only here because ALSA _thinks_ it needs them...
  */
@@ -219,6 +252,9 @@ extern void __iounmap(void __iomem *addr);
 #define ioremap(offset, size)                  \
        __ioremap((offset), (size), 0)
 
+#define ioremap_nocache(offset, size)          \
+       __ioremap((offset), (size), 0)
+
 #define iounmap(addr)                          \
        __iounmap(addr)
 
@@ -230,6 +266,14 @@ extern void __iounmap(void __iomem *addr);
 #define page_to_bus page_to_phys
 #define bus_to_page phys_to_page
 
+/*
+ * Create a virtual mapping cookie for an IO port range.  There exists
+ * no such thing as port-based I/O on AVR32, so a regular ioremap()
+ * should do what we need.
+ */
+#define ioport_map(port, nr)   ioremap(port, nr)
+#define ioport_unmap(port)     iounmap(port)
+
 #define dma_cache_wback_inv(_start, _size)     \
        flush_dcache_region(_start, _size)
 #define dma_cache_inv(_start, _size)           \