Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

[linux-2.6] / include / asm-arm / arch-s3c2410 / regs-mem.h

diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h
index a2d7d0cec04234b08b9fa5187dd0c70f5b9e33f1..312ff93b63c6da560dcf21967cda4f1488b76eca 100644 (file)
--- a/include/asm-arm/arch-s3c2410/regs-mem.h
+++ b/include/asm-arm/arch-s3c2410/regs-mem.h
@@ -8,12 +8,6 @@
  * published by the Free Software Foundation.
  *
  * S3C2410 Memory Control register definitions
- *
- *  Changelog:
- *     29-Sep-2004  BJD  Initial include for Linux
- *      10-Mar-2005  LCVR Changed S3C2410_VA to S3C24XX_VA
- *      04-Apr-2005  LCVR Added S3C2400 DRAM/BANKSIZE_MASK definitions
- *
 */
 
 #ifndef __ASM_ARM_MEMREGS_H
@@ -104,16 +98,19 @@
 #define S3C2410_BANKCON_Tacp3          (0x1 << 2)
 #define S3C2410_BANKCON_Tacp4          (0x2 << 2)
 #define S3C2410_BANKCON_Tacp6          (0x3 << 2)
+#define S3C2410_BANKCON_Tacp_SHIFT     (2)
 
 #define S3C2410_BANKCON_Tcah0          (0x0 << 4)
 #define S3C2410_BANKCON_Tcah1          (0x1 << 4)
 #define S3C2410_BANKCON_Tcah2          (0x2 << 4)
 #define S3C2410_BANKCON_Tcah4          (0x3 << 4)
+#define S3C2410_BANKCON_Tcah_SHIFT     (4)
 
 #define S3C2410_BANKCON_Tcoh0          (0x0 << 6)
 #define S3C2410_BANKCON_Tcoh1          (0x1 << 6)
 #define S3C2410_BANKCON_Tcoh2          (0x2 << 6)
 #define S3C2410_BANKCON_Tcoh4          (0x3 << 6)
+#define S3C2410_BANKCON_Tcoh_SHIFT     (6)
 
 #define S3C2410_BANKCON_Tacc1          (0x0 << 8)
 #define S3C2410_BANKCON_Tacc2          (0x1 << 8)
@@ -123,26 +120,29 @@
 #define S3C2410_BANKCON_Tacc8          (0x5 << 8)
 #define S3C2410_BANKCON_Tacc10         (0x6 << 8)
 #define S3C2410_BANKCON_Tacc14         (0x7 << 8)
+#define S3C2410_BANKCON_Tacc_SHIFT     (8)
 
 #define S3C2410_BANKCON_Tcos0          (0x0 << 11)
 #define S3C2410_BANKCON_Tcos1          (0x1 << 11)
 #define S3C2410_BANKCON_Tcos2          (0x2 << 11)
 #define S3C2410_BANKCON_Tcos4          (0x3 << 11)
+#define S3C2410_BANKCON_Tcos_SHIFT     (11)
 
 #define S3C2410_BANKCON_Tacs0          (0x0 << 13)
 #define S3C2410_BANKCON_Tacs1          (0x1 << 13)
 #define S3C2410_BANKCON_Tacs2          (0x2 << 13)
 #define S3C2410_BANKCON_Tacs4          (0x3 << 13)
+#define S3C2410_BANKCON_Tacs_SHIFT     (13)
 
 #define S3C2410_BANKCON_SRAM           (0x0 << 15)
 #define S3C2400_BANKCON_EDODRAM                (0x2 << 15)
 #define S3C2410_BANKCON_SDRAM          (0x3 << 15)
 
 /* next bits only for EDO DRAM in 6,7 */
-#define S3C2400_BANKCON_EDO_Trdc1      (0x00 << 4)
-#define S3C2400_BANKCON_EDO_Trdc2      (0x01 << 4)
-#define S3C2400_BANKCON_EDO_Trdc3      (0x02 << 4)
-#define S3C2400_BANKCON_EDO_Trdc4      (0x03 << 4)
+#define S3C2400_BANKCON_EDO_Trcd1      (0x00 << 4)
+#define S3C2400_BANKCON_EDO_Trcd2      (0x01 << 4)
+#define S3C2400_BANKCON_EDO_Trcd3      (0x02 << 4)
+#define S3C2400_BANKCON_EDO_Trcd4      (0x03 << 4)
 
 /* CAS pulse width */
 #define S3C2400_BANKCON_EDO_PULSE1     (0x00 << 3)
@@ -159,9 +159,9 @@
 #define S3C2400_BANKCON_EDO_SCANb11    (0x03 << 0)
 
 /* next bits only for SDRAM in 6,7 */
-#define S3C2410_BANKCON_Trdc2          (0x00 << 2)
-#define S3C2410_BANKCON_Trdc3          (0x01 << 2)
-#define S3C2410_BANKCON_Trdc4          (0x02 << 2)
+#define S3C2410_BANKCON_Trcd2          (0x00 << 2)
+#define S3C2410_BANKCON_Trcd3          (0x01 << 2)
+#define S3C2410_BANKCON_Trcd4          (0x02 << 2)
 
 /* control column address select */
 #define S3C2410_BANKCON_SCANb8         (0x00 << 0)