Merge git://git.infradead.org/mtd-2.6

[linux-2.6] / include / asm-arm / arch-realview / entry-macro.S

diff --git a/include/asm-arm/arch-realview/entry-macro.S b/include/asm-arm/arch-realview/entry-macro.S
index 4df469bf42e2809b84bddce343728b08af3488af..cd26306d8e57f8d2ecff1361ece23315485473d8 100644 (file)
--- a/include/asm-arm/arch-realview/entry-macro.S
+++ b/include/asm-arm/arch-realview/entry-macro.S
@@ -7,12 +7,20 @@
  * License version 2. This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-
+#include <asm/hardware.h>
 #include <asm/hardware/gic.h>
 
                .macro  disable_fiq
                .endm
 
+               .macro  get_irqnr_preamble, base, tmp
+               ldr     \base, =gic_cpu_base_addr
+               ldr     \base, [\base]
+               .endm
+
+               .macro  arch_ret_to_user, tmp1, tmp2
+               .endm
+
                /*
                 * The interrupt numbering scheme is defined in the
                 * interrupt controller spec.  To wit:
@@ -34,7 +42,6 @@
 
                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
 
-               ldr     \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
                ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
 
                ldr     \tmp, =1021
@@ -61,3 +68,14 @@
                strcc   \irqstat, [\base, #GIC_CPU_EOI]
                cmpcs   \irqnr, \irqnr
                .endm
+
+               /* As above, this assumes that irqstat and base are preserved.. */
+
+               .macro test_for_ltirq, irqnr, irqstat, base, tmp
+               bic     \irqnr, \irqstat, #0x1c00
+               mov     \tmp, #0
+               cmp     \irqnr, #29
+               moveq   \tmp, #1
+               streq   \irqstat, [\base, #GIC_CPU_EOI]
+               cmp     \tmp, #0
+               .endm