[ARM] 3919/1: Fixed definition of some PXA270 CIF related registers

[linux-2.6] / include / asm-arm / arch-pxa / pxa-regs.h

diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 9f83f4adfbf3592331b40713c563158bea6ced22..cff752f35230766554a28d9c7241704a9b5e37a0 100644 (file)
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1329,6 +1329,7 @@
 #define GPIO84_NSRXD           84      /* NSSP receive */
 #define GPIO85_nPCE_1          85      /* Card Enable for Card Space (PXA27x) */
 #define GPIO92_MMCDAT0         92      /* MMC DAT0 (PXA27x) */
+#define GPIO102_nPCE_1         102     /* PCMCIA (PXA27x) */
 #define GPIO109_MMCDAT1                109     /* MMC DAT1 (PXA27x) */
 #define GPIO110_MMCDAT2                110     /* MMC DAT2 (PXA27x) */
 #define GPIO110_MMCCS0         110     /* MMC Chip Select 0 (PXA27x) */
@@ -1471,6 +1472,7 @@
 #define GPIO84_NSSP_RX         (84 | GPIO_ALT_FN_2_IN)
 #define GPIO85_nPCE_1_MD       (85 | GPIO_ALT_FN_1_OUT)
 #define GPIO92_MMCDAT0_MD      (92 | GPIO_ALT_FN_1_OUT)
+#define GPIO102_nPCE_1_MD      (102 | GPIO_ALT_FN_1_OUT)
 #define GPIO104_pSKTSEL_MD     (104 | GPIO_ALT_FN_1_OUT)
 #define GPIO109_MMCDAT1_MD     (109 | GPIO_ALT_FN_1_OUT)
 #define GPIO110_MMCDAT2_MD     (110 | GPIO_ALT_FN_1_OUT)
@@ -1679,6 +1681,7 @@
 #define SSSR_TINT              (1 << 19)       /* Receiver Time-out Interrupt */
 #define SSSR_PINT              (1 << 18)       /* Peripheral Trailing Byte Interrupt */
 
+#define SSPSP_FSRT             (1 << 25)       /* Frame Sync Relative Timing */
 #define SSPSP_DMYSTOP(x)       (x << 23)       /* Dummy Stop */
 #define SSPSP_SFRMWDTH(x)      (x << 16)       /* Serial Frame Width */
 #define SSPSP_SFRMDLY(x)       (x << 9)        /* Serial Frame Delay */
@@ -2239,7 +2242,7 @@
 
 #define CICR1_TBIT     (1 << 31)       /* Transparency bit */
 #define CICR1_RGBT_CONV        (0x3 << 30)     /* RGBT conversion mask */
-#define CICR1_PPL      (0x3f << 15)    /* Pixels per line mask */
+#define CICR1_PPL      (0x7ff << 15)   /* Pixels per line mask */
 #define CICR1_RGB_CONV (0x7 << 12)     /* RGB conversion mask */
 #define CICR1_RGB_F    (1 << 11)       /* RGB format */
 #define CICR1_YCBCR_F  (1 << 10)       /* YCbCr format */
@@ -2265,7 +2268,7 @@
 #define CICR3_VSW      (0x3f << 10)    /* Vertical sync pulse width mask */
 #define CICR3_BFPW     (0x3f << 3)     /* Beginning-of-frame pixel clock
                                           wait count mask */
-#define CICR3_LPF      (0x3ff << 0)    /* Lines per frame mask */
+#define CICR3_LPF      (0x7ff << 0)    /* Lines per frame mask */
 
 #define CICR4_MCLK_DLY (0x3 << 24)     /* MCLK Data Capture Delay mask */
 #define CICR4_PCLK_EN  (1 << 23)       /* Pixel clock enable */
@@ -2286,8 +2289,8 @@
 #define CISR_EOL       (1 << 8)        /* End of line */
 #define CISR_PAR_ERR   (1 << 7)        /* Parity error */
 #define CISR_CQD       (1 << 6)        /* Camera interface quick disable */
-#define CISR_SOF       (1 << 5)        /* Start of frame */
-#define CISR_CDD       (1 << 4)        /* Camera interface disable done */
+#define CISR_CDD       (1 << 5)        /* Camera interface disable done */
+#define CISR_SOF       (1 << 4)        /* Start of frame */
 #define CISR_EOF       (1 << 3)        /* End of frame */
 #define CISR_IFO_2     (1 << 2)        /* FIFO overrun for Channel 2 */
 #define CISR_IFO_1     (1 << 1)        /* FIFO overrun for Channel 1 */