MXC arch: Simplify architecture's irq sources

[linux-2.6] / include / asm-arm / arch-mxc / mxc.h

diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 1df4e2f249204ded68246fe84dee74db8de9fc72..3e1c4ded18e2811610508c2ee5687e4014c8403a 100644 (file)
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -29,42 +29,4 @@
 # define cpu_is_mx31() (0)
 #endif
 
-/*
- *****************************************
- * AVIC Registers                        *
- *****************************************
- */
-#define AVIC_BASE              IO_ADDRESS(AVIC_BASE_ADDR)
-#define AVIC_INTCNTL           (AVIC_BASE + 0x00)      /* int control reg */
-#define AVIC_NIMASK            (AVIC_BASE + 0x04)      /* int mask reg */
-#define AVIC_INTENNUM          (AVIC_BASE + 0x08)      /* int enable number reg */
-#define AVIC_INTDISNUM         (AVIC_BASE + 0x0C)      /* int disable number reg */
-#define AVIC_INTENABLEH                (AVIC_BASE + 0x10)      /* int enable reg high */
-#define AVIC_INTENABLEL                (AVIC_BASE + 0x14)      /* int enable reg low */
-#define AVIC_INTTYPEH          (AVIC_BASE + 0x18)      /* int type reg high */
-#define AVIC_INTTYPEL          (AVIC_BASE + 0x1C)      /* int type reg low */
-#define AVIC_NIPRIORITY7       (AVIC_BASE + 0x20)      /* norm int priority lvl7 */
-#define AVIC_NIPRIORITY6       (AVIC_BASE + 0x24)      /* norm int priority lvl6 */
-#define AVIC_NIPRIORITY5       (AVIC_BASE + 0x28)      /* norm int priority lvl5 */
-#define AVIC_NIPRIORITY4       (AVIC_BASE + 0x2C)      /* norm int priority lvl4 */
-#define AVIC_NIPRIORITY3       (AVIC_BASE + 0x30)      /* norm int priority lvl3 */
-#define AVIC_NIPRIORITY2       (AVIC_BASE + 0x34)      /* norm int priority lvl2 */
-#define AVIC_NIPRIORITY1       (AVIC_BASE + 0x38)      /* norm int priority lvl1 */
-#define AVIC_NIPRIORITY0       (AVIC_BASE + 0x3C)      /* norm int priority lvl0 */
-#define AVIC_NIVECSR           (AVIC_BASE + 0x40)      /* norm int vector/status */
-#define AVIC_FIVECSR           (AVIC_BASE + 0x44)      /* fast int vector/status */
-#define AVIC_INTSRCH           (AVIC_BASE + 0x48)      /* int source reg high */
-#define AVIC_INTSRCL           (AVIC_BASE + 0x4C)      /* int source reg low */
-#define AVIC_INTFRCH           (AVIC_BASE + 0x50)      /* int force reg high */
-#define AVIC_INTFRCL           (AVIC_BASE + 0x54)      /* int force reg low */
-#define AVIC_NIPNDH            (AVIC_BASE + 0x58)      /* norm int pending high */
-#define AVIC_NIPNDL            (AVIC_BASE + 0x5C)      /* norm int pending low */
-#define AVIC_FIPNDH            (AVIC_BASE + 0x60)      /* fast int pending high */
-#define AVIC_FIPNDL            (AVIC_BASE + 0x64)      /* fast int pending low */
-
-#define SYSTEM_PREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x20)
-#define SYSTEM_SREV_REG                IO_ADDRESS(IIM_BASE_ADDR + 0x24)
-#define IIM_PROD_REV_SH                3
-#define IIM_PROD_REV_LEN       5
-
 #endif /*  __ASM_ARCH_MXC_H__ */