netfilter: nf_nat_snmp_basic: fix a range check in NAT for SNMP

[linux-2.6] / include / asm-arm / arch-ixp2000 / ixp2000-regs.h

diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 32aece069869b52c0aede2617fdbec8ee898fda1..ccae4bec92c58337b05c535ee17c2bd94b66d3f2 100644 (file)
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -26,6 +26,8 @@
  * fc000000    da000000        16M             PCI CFG0
  * fd000000    d8000000        16M             PCI I/O
  * fe[0-7]00000                        8M              per-platform mappings
+ * fe900000    80000000        1M              SRAM #0 (first MB)
+ * fea00000    cb400000        1M              SCRATCH ring get/put
  * feb00000    c8000000        1M              MSF
  * fec00000    df000000        1M              PCI CSRs
  * fed00000    de000000        1M              PCI CREG
@@ -59,14 +61,15 @@
 #define        IXP2000_CAP_SIZE                0x00100000
 
 /*
- * Addresses for specific on-chip peripherals
+ * Addresses for specific on-chip peripherals.
  */
 #define        IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfef80000
 #define        IXP2000_GLOBAL_REG_VIRT_BASE    0xfef04000
 #define        IXP2000_UART_PHYS_BASE          0xc0030000
 #define        IXP2000_UART_VIRT_BASE          0xfef30000
 #define        IXP2000_TIMER_VIRT_BASE         0xfef20000
-#define        IXP2000_GPIO_VIRT_BASE          0Xfef10000
+#define        IXP2000_UENGINE_CSR_VIRT_BASE   0xfef18000
+#define        IXP2000_GPIO_VIRT_BASE          0xfef10000
 
 /*
  * Devices outside of the 0xc0000000 -> 0xc0100000 range.  The virtual
@@ -90,6 +93,14 @@
 #define IXP2000_MSF_VIRT_BASE          0xfeb00000
 #define IXP2000_MSF_SIZE               0x00100000
 
+#define IXP2000_SCRATCH_RING_PHYS_BASE 0xcb400000
+#define IXP2000_SCRATCH_RING_VIRT_BASE 0xfea00000
+#define IXP2000_SCRATCH_RING_SIZE      0x00100000
+
+#define IXP2000_SRAM0_PHYS_BASE                0x80000000
+#define IXP2000_SRAM0_VIRT_BASE                0xfe900000
+#define IXP2000_SRAM0_SIZE             0x00100000
+
 #define IXP2000_PCI_IO_PHYS_BASE       0xd8000000
 #define        IXP2000_PCI_IO_VIRT_BASE        0xfd000000
 #define IXP2000_PCI_IO_SIZE            0x01000000
@@ -155,6 +166,14 @@
 #define IXP2000_IRQ_THD_RAW_STATUS_B_1 IXP2000_INTCTL_REG(0x84)
 #define IXP2000_IRQ_THD_RAW_STATUS_B_2 IXP2000_INTCTL_REG(0x88)
 #define IXP2000_IRQ_THD_RAW_STATUS_B_3 IXP2000_INTCTL_REG(0x8c)
+#define IXP2000_IRQ_THD_STATUS_A_0     IXP2000_INTCTL_REG(0xe0)
+#define IXP2000_IRQ_THD_STATUS_A_1     IXP2000_INTCTL_REG(0xe4)
+#define IXP2000_IRQ_THD_STATUS_A_2     IXP2000_INTCTL_REG(0xe8)
+#define IXP2000_IRQ_THD_STATUS_A_3     IXP2000_INTCTL_REG(0xec)
+#define IXP2000_IRQ_THD_STATUS_B_0     IXP2000_INTCTL_REG(0x100)
+#define IXP2000_IRQ_THD_STATUS_B_1     IXP2000_INTCTL_REG(0x104)
+#define IXP2000_IRQ_THD_STATUS_B_2     IXP2000_INTCTL_REG(0x108)
+#define IXP2000_IRQ_THD_STATUS_B_3     IXP2000_INTCTL_REG(0x10c)
 #define IXP2000_IRQ_THD_ENABLE_SET_A_0 IXP2000_INTCTL_REG(0x160)
 #define IXP2000_IRQ_THD_ENABLE_SET_A_1 IXP2000_INTCTL_REG(0x164)
 #define IXP2000_IRQ_THD_ENABLE_SET_A_2 IXP2000_INTCTL_REG(0x168)
@@ -252,7 +271,7 @@
 #define IXP2000_PCI_XSCALE_INT_ENABLE  IXP2000_PCI_CSR(0x15C)
 
 #define IXP2000_PCICNTL_PNR            (1<<17) /* PCI not Reset bit of PCI_CONTROL */
-#define IXP2000_PCICNTL_PCF            (1<<28) /* PCI Centrolfunction bit */
+#define IXP2000_PCICNTL_PCF            (1<<28) /* PCI Central function bit */
 #define IXP2000_XSCALE_INT             (1<<1)  /* Interrupt from XScale to PCI */
 
 /* These are from the IRQ register in the PCI ISR register */
@@ -334,8 +353,8 @@
  * Masks and shifts for various fields in the WTC and RTC registers.
  */
 #define        SLOWPORT_WRTC_MASK_HD           0x0003
-#define        SLOWPORT_WRTC_MASK_SU           0x003c
-#define        SLOWPORT_WRTC_MASK_PW           0x03c0
+#define        SLOWPORT_WRTC_MASK_PW           0x003c
+#define        SLOWPORT_WRTC_MASK_SU           0x03c0
 
 #define        SLOWPORT_WRTC_SHIFT_HD          0x00
 #define        SLOWPORT_WRTC_SHIFT_SU          0x02
@@ -392,4 +411,47 @@
 #define        WDT_RESET_ENABLE                0x01000000
 
 
+/*
+ * MSF registers.  The IXP2400 and IXP2800 have somewhat different MSF
+ * units, but the registers that differ between the two don't overlap,
+ * so we can have one register list for both.
+ */
+#define IXP2000_MSF_REG(x)                     ((volatile unsigned long*)(IXP2000_MSF_VIRT_BASE + (x)))
+#define IXP2000_MSF_RX_CONTROL                 IXP2000_MSF_REG(0x0000)
+#define IXP2000_MSF_TX_CONTROL                 IXP2000_MSF_REG(0x0004)
+#define IXP2000_MSF_INTERRUPT_STATUS           IXP2000_MSF_REG(0x0008)
+#define IXP2000_MSF_INTERRUPT_ENABLE           IXP2000_MSF_REG(0x000c)
+#define IXP2000_MSF_CSIX_TYPE_MAP              IXP2000_MSF_REG(0x0010)
+#define IXP2000_MSF_FC_EGRESS_STATUS           IXP2000_MSF_REG(0x0014)
+#define IXP2000_MSF_FC_INGRESS_STATUS          IXP2000_MSF_REG(0x0018)
+#define IXP2000_MSF_HWM_CONTROL                        IXP2000_MSF_REG(0x0024)
+#define IXP2000_MSF_FC_STATUS_OVERRIDE         IXP2000_MSF_REG(0x0028)
+#define IXP2000_MSF_CLOCK_CONTROL              IXP2000_MSF_REG(0x002c)
+#define IXP2000_MSF_RX_PORT_MAP                        IXP2000_MSF_REG(0x0040)
+#define IXP2000_MSF_RBUF_ELEMENT_DONE          IXP2000_MSF_REG(0x0044)
+#define IXP2000_MSF_RX_MPHY_POLL_LIMIT         IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_CALENDAR_LENGTH         IXP2000_MSF_REG(0x0048)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_0       IXP2000_MSF_REG(0x0050)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_1       IXP2000_MSF_REG(0x0054)
+#define IXP2000_MSF_RX_THREAD_FREELIST_TIMEOUT_2       IXP2000_MSF_REG(0x0058)
+#define IXP2000_MSF_TX_SEQUENCE_0              IXP2000_MSF_REG(0x0060)
+#define IXP2000_MSF_TX_SEQUENCE_1              IXP2000_MSF_REG(0x0064)
+#define IXP2000_MSF_TX_SEQUENCE_2              IXP2000_MSF_REG(0x0068)
+#define IXP2000_MSF_TX_MPHY_POLL_LIMIT         IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_TX_CALENDAR_LENGTH         IXP2000_MSF_REG(0x0070)
+#define IXP2000_MSF_RX_UP_CONTROL_0            IXP2000_MSF_REG(0x0080)
+#define IXP2000_MSF_RX_UP_CONTROL_1            IXP2000_MSF_REG(0x0084)
+#define IXP2000_MSF_RX_UP_CONTROL_2            IXP2000_MSF_REG(0x0088)
+#define IXP2000_MSF_RX_UP_CONTROL_3            IXP2000_MSF_REG(0x008c)
+#define IXP2000_MSF_TX_UP_CONTROL_0            IXP2000_MSF_REG(0x0090)
+#define IXP2000_MSF_TX_UP_CONTROL_1            IXP2000_MSF_REG(0x0094)
+#define IXP2000_MSF_TX_UP_CONTROL_2            IXP2000_MSF_REG(0x0098)
+#define IXP2000_MSF_TX_UP_CONTROL_3            IXP2000_MSF_REG(0x009c)
+#define IXP2000_MSF_TRAIN_DATA                 IXP2000_MSF_REG(0x00a0)
+#define IXP2000_MSF_TRAIN_CALENDAR             IXP2000_MSF_REG(0x00a4)
+#define IXP2000_MSF_TRAIN_FLOW_CONTROL         IXP2000_MSF_REG(0x00a8)
+#define IXP2000_MSF_TX_CALENDAR_0              IXP2000_MSF_REG(0x1000)
+#define IXP2000_MSF_RX_PORT_CALENDAR_STATUS    IXP2000_MSF_REG(0x1400)
+
+
 #endif                         /* _IXP2000_H_ */