Merge master.kernel.org:/pub/scm/linux/kernel/git/lenb/to-linus

[linux-2.6] / include / asm-arm / arch-ixp2000 / ixp2000-regs.h

diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index a1d9e181b10f1c1d579cf4b3fa4d30db1a39b9a5..75623f81ef75492801108bb895f745fdbdb962e4 100644 (file)
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -18,6 +18,21 @@
 #ifndef _IXP2000_REGS_H_
 #define _IXP2000_REGS_H_
 
+/*
+ * IXP2000 linux memory map:
+ *
+ * virt                phys            size
+ * fb000000    db000000        16M             PCI CFG1
+ * fc000000    da000000        16M             PCI CFG0
+ * fd000000    d8000000        16M             PCI I/O
+ * fe[0-7]00000                        8M              per-platform mappings
+ * feb00000    c8000000        1M              MSF
+ * fec00000    df000000        1M              PCI CSRs
+ * fed00000    de000000        1M              PCI CREG
+ * fee00000    d6000000        1M              INTCTL
+ * fef00000    c0000000        1M              CAP
+ */
+
 /* 
  * Static I/O regions.
  *
@@ -71,6 +86,10 @@
 #define        IXP2000_PCI_CSR_VIRT_BASE       0xfec00000
 #define        IXP2000_PCI_CSR_SIZE            0x00100000
 
+#define IXP2000_MSF_PHYS_BASE          0xc8000000
+#define IXP2000_MSF_VIRT_BASE          0xfeb00000
+#define IXP2000_MSF_SIZE               0x00100000
+
 #define IXP2000_PCI_IO_PHYS_BASE       0xd8000000
 #define        IXP2000_PCI_IO_VIRT_BASE        0xfd000000
 #define IXP2000_PCI_IO_SIZE            0x01000000
@@ -241,7 +260,7 @@
 #define PCI_CONTROL_BE_DEI             (1 << 21)       /* Big Endian Data Enable In  */
 #define PCI_CONTROL_BE_BEO             (1 << 20)       /* Big Endian Byte Enable Out */
 #define PCI_CONTROL_BE_BEI             (1 << 19)       /* Big Endian Byte Enable In  */
-#define PCI_CONTROL_PNR                        (1 << 17)       /* PCI Not Reset bit */
+#define PCI_CONTROL_IEE                        (1 << 17)       /* I/O cycle Endian swap Enable */
 
 #define IXP2000_PCI_RST_REL            (1 << 2)
 #define CFG_RST_DIR                    (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)