*
* 2004-12-04: Arnaud Patard <arnaud.patard@rtp-net.org>
* - Added the possibility to set on or off the
- * debugging mesaages
+ * debugging messages
* - Replaced 0 and 1 by on or off when reading the
* /sys files
*
* - add pixel clock divisor control
*
* 2004-11-11: Arnaud Patard <arnaud.patard@rtp-net.org>
- * - Removed the use of currcon as it no more exist
+ * - Removed the use of currcon as it no more exists
* - Added LCD power sysfs interface
*
* 2004-11-03: Ben Dooks <ben-linux@fluff.org>
* - Add support for different devices
* - Backlight support
*
- * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
+ * 2004-09-05: Herbert Pötzl <herbert@13thfloor.at>
* - added clock (de-)allocation code
* - added fixem fbmem option
*
* - code cleanup
* - added a forgotten return in h1940fb_init
*
- * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
+ * 2004-07-19: Herbert Pötzl <herbert@13thfloor.at>
* - code cleanup and extended debugging
*
* 2004-07-15: Arnaud Patard <arnaud.patard@rtp-net.org>
#include <linux/init.h>
#include <linux/dma-mapping.h>
#include <linux/interrupt.h>
-#include <linux/workqueue.h>
-#include <linux/wait.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <asm/io.h>
-#include <asm/uaccess.h>
#include <asm/div64.h>
#include <asm/mach/map.h>
#include "s3c2410fb.h"
-static struct s3c2410fb_mach_info *mach_info;
-
/* Debugging stuff */
#ifdef CONFIG_FB_S3C2410_DEBUG
static int debug = 1;
static void s3c2410fb_set_lcdaddr(struct fb_info *info)
{
unsigned long saddr1, saddr2, saddr3;
- int line_length = info->var.xres * info->var.bits_per_pixel;
+ struct s3c2410fb_info *fbi = info->par;
+ void __iomem *regs = fbi->io;
saddr1 = info->fix.smem_start >> 1;
saddr2 = info->fix.smem_start;
- saddr2 += (line_length * info->var.yres) / 8;
+ saddr2 += info->fix.line_length * info->var.yres;
saddr2 >>= 1;
saddr3 = S3C2410_OFFSIZE(0) |
- S3C2410_PAGEWIDTH((line_length / 16) & 0x3ff);
+ S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
- writel(saddr1, S3C2410_LCDSADDR1);
- writel(saddr2, S3C2410_LCDSADDR2);
- writel(saddr3, S3C2410_LCDSADDR3);
+ writel(saddr1, regs + S3C2410_LCDSADDR1);
+ writel(saddr2, regs + S3C2410_LCDSADDR2);
+ writel(saddr3, regs + S3C2410_LCDSADDR3);
}
/* s3c2410fb_calc_pixclk()
unsigned long clk = clk_get_rate(fbi->clk);
unsigned long long div;
- /* pixclk is in picoseoncds, our clock is in Hz
+ /* pixclk is in picoseconds, our clock is in Hz
*
* Hz -> picoseconds is / 10^-12
*/
div = (unsigned long long)clk * pixclk;
- do_div(div, 1000000UL);
- do_div(div, 1000000UL);
+ div >>= 12; /* div / 2^12 */
+ do_div(div, 625 * 625UL * 625); /* div / 5^12 */
dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
return div;
struct fb_info *info)
{
struct s3c2410fb_info *fbi = info->par;
- struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
+ struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
struct s3c2410fb_display *display = NULL;
+ struct s3c2410fb_display *default_display = mach_info->displays +
+ mach_info->default_display;
+ int type = default_display->type;
unsigned i;
dprintk("check_var(var=%p, info=%p)\n", var, info);
/* validate x/y resolution */
-
- for (i = 0; i < mach_info->num_displays; i++)
- if (var->yres == mach_info->displays[i].yres &&
- var->xres == mach_info->displays[i].xres &&
- var->bits_per_pixel == mach_info->displays[i].bpp) {
- display = mach_info->displays + i;
- fbi->current_display = i;
- break;
- }
+ /* choose default mode if possible */
+ if (var->yres == default_display->yres &&
+ var->xres == default_display->xres &&
+ var->bits_per_pixel == default_display->bpp)
+ display = default_display;
+ else
+ for (i = 0; i < mach_info->num_displays; i++)
+ if (type == mach_info->displays[i].type &&
+ var->yres == mach_info->displays[i].yres &&
+ var->xres == mach_info->displays[i].xres &&
+ var->bits_per_pixel == mach_info->displays[i].bpp) {
+ display = mach_info->displays + i;
+ break;
+ }
if (!display) {
dprintk("wrong resolution or depth %dx%d at %d bpp\n",
/* it is always the size as the display */
var->xres_virtual = display->xres;
var->yres_virtual = display->yres;
+ var->height = display->height;
+ var->width = display->width;
/* copy lcd settings */
+ var->pixclock = display->pixclock;
var->left_margin = display->left_margin;
var->right_margin = display->right_margin;
+ var->upper_margin = display->upper_margin;
+ var->lower_margin = display->lower_margin;
+ var->vsync_len = display->vsync_len;
+ var->hsync_len = display->hsync_len;
+
+ fbi->regs.lcdcon5 = display->lcdcon5;
+ /* set display type */
+ fbi->regs.lcdcon1 = display->type;
var->transp.offset = 0;
var->transp.length = 0;
var->blue.length = 5;
}
break;
- case 24:
- /* 24 bpp 888 */
+ case 32:
+ /* 24 bpp 888 and 8 dummy */
var->red.length = 8;
var->red.offset = 16;
var->green.length = 8;
var->blue.length = 8;
var->blue.offset = 0;
break;
-
-
}
return 0;
}
int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
int hs = var->xres >> 2;
unsigned wdly = (var->left_margin >> 4) - 1;
-
- dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
- dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
- dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
+ unsigned wlh = (var->hsync_len >> 4) - 1;
if (type != S3C2410_LCDCON1_STN4)
hs >>= 1;
- regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
-
switch (var->bits_per_pixel) {
case 1:
regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
var->bits_per_pixel);
}
/* update X/Y info */
- dprintk("setting vert: up=%d, low=%d, sync=%d\n",
- var->upper_margin, var->lower_margin, var->vsync_len);
-
dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
var->left_margin, var->right_margin, var->hsync_len);
- regs->lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
- regs->lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
+ regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
if (wdly > 3)
wdly = 3;
+ if (wlh > 3)
+ wlh = 3;
+
regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
S3C2410_LCDCON3_HOZVAL(hs - 1);
+
+ regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
}
/* s3c2410fb_calculate_tft_lcd_regs
const struct s3c2410fb_info *fbi = info->par;
const struct fb_var_screeninfo *var = &info->var;
- dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
- dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
- dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
-
- regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
-
switch (var->bits_per_pixel) {
case 1:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
break;
case 8:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_FRM565;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
break;
case 16:
regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
+ regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
+ regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
+ break;
+ case 32:
+ regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
+ regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
+ S3C2410_LCDCON5_HWSWP |
+ S3C2410_LCDCON5_BPP24BL);
break;
-
default:
/* invalid pixel depth */
dev_err(fbi->dev, "invalid bpp %d\n",
dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
var->left_margin, var->right_margin, var->hsync_len);
- regs->lcdcon2 &= ~S3C2410_LCDCON2_LINEVAL(0x3ff);
- regs->lcdcon2 |= S3C2410_LCDCON2_LINEVAL(var->yres - 1);
+ regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
+ S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
+ S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
+ S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
S3C2410_LCDCON3_HOZVAL(var->xres - 1);
+
+ regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
}
/* s3c2410fb_activate_var
static void s3c2410fb_activate_var(struct fb_info *info)
{
struct s3c2410fb_info *fbi = info->par;
+ void __iomem *regs = fbi->io;
+ int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
struct fb_var_screeninfo *var = &info->var;
- struct s3c2410fb_mach_info *mach_info = fbi->mach_info;
- struct s3c2410fb_display *display = mach_info->displays +
- fbi->current_display;
-
- /* set display type */
- fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_TFT;
- fbi->regs.lcdcon1 |= display->type;
-
- /* check to see if we need to update sync/borders */
-
- if (!mach_info->fixed_syncs) {
- fbi->regs.lcdcon2 =
- S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
- S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
- S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
-
- fbi->regs.lcdcon4 &= ~S3C2410_LCDCON4_HSPW(0xff);
- fbi->regs.lcdcon4 |= S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
- }
-
- if (var->pixclock > 0) {
- int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
-
- if (display->type == S3C2410_LCDCON1_TFT) {
- clkdiv = (clkdiv / 2) - 1;
- if (clkdiv < 0)
- clkdiv = 0;
- } else {
- clkdiv = (clkdiv / 2);
- if (clkdiv < 2)
- clkdiv = 2;
- }
+ int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
- fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
- fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
- }
+ dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
+ dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
+ dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
- if (display->type == S3C2410_LCDCON1_TFT)
+ if (type == S3C2410_LCDCON1_TFT) {
s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
- else
+ --clkdiv;
+ if (clkdiv < 0)
+ clkdiv = 0;
+ } else {
s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
+ if (clkdiv < 2)
+ clkdiv = 2;
+ }
+
+ fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
/* write new registers */
dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
- writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID, S3C2410_LCDCON1);
- writel(fbi->regs.lcdcon2, S3C2410_LCDCON2);
- writel(fbi->regs.lcdcon3, S3C2410_LCDCON3);
- writel(fbi->regs.lcdcon4, S3C2410_LCDCON4);
- writel(fbi->regs.lcdcon5, S3C2410_LCDCON5);
+ writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
+ regs + S3C2410_LCDCON1);
+ writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
+ writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
+ writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
+ writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
/* set lcd address pointers */
s3c2410fb_set_lcdaddr(info);
- writel(fbi->regs.lcdcon1, S3C2410_LCDCON1);
+ fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
+ writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
}
/*
struct fb_var_screeninfo *var = &info->var;
switch (var->bits_per_pixel) {
+ case 32:
case 16:
+ case 12:
info->fix.visual = FB_VISUAL_TRUECOLOR;
break;
case 1:
break;
}
- info->fix.line_length = (var->width * var->bits_per_pixel) / 8;
+ info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
/* activate this new configuration */
unsigned transp, struct fb_info *info)
{
struct s3c2410fb_info *fbi = info->par;
+ void __iomem *regs = fbi->io;
unsigned int val;
/* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
if (regno < 256) {
/* currently assume RGB 5-6-5 mode */
- val = ((red >> 0) & 0xf800);
- val |= ((green >> 5) & 0x07e0);
- val |= ((blue >> 11) & 0x001f);
+ val = (red >> 0) & 0xf800;
+ val |= (green >> 5) & 0x07e0;
+ val |= (blue >> 11) & 0x001f;
- writel(val, S3C2410_TFTPAL(regno));
+ writel(val, regs + S3C2410_TFTPAL(regno));
schedule_palette_update(fbi, regno, val);
}
*/
static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
{
- dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
+ struct s3c2410fb_info *fbi = info->par;
+ void __iomem *regs = fbi->io;
- if (mach_info == NULL)
- return -EINVAL;
+ dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
if (blank_mode == FB_BLANK_UNBLANK)
- writel(0x0, S3C2410_TPAL);
+ writel(0x0, regs + S3C2410_TPAL);
else {
dprintk("setting TPAL to output 0x000000\n");
- writel(S3C2410_TPAL_EN, S3C2410_TPAL);
+ writel(S3C2410_TPAL_EN, regs + S3C2410_TPAL);
}
return 0;
{
return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
}
+
static int s3c2410fb_debug_store(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
{
- if (mach_info == NULL)
- return -EINVAL;
-
if (len < 1)
return -EINVAL;
static int __init s3c2410fb_map_video_memory(struct fb_info *info)
{
struct s3c2410fb_info *fbi = info->par;
+ dma_addr_t map_dma;
+ unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
dprintk("map_video_memory(fbi=%p)\n", fbi);
- fbi->map_size = PAGE_ALIGN(info->fix.smem_len + PAGE_SIZE);
- fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
- &fbi->map_dma, GFP_KERNEL);
+ info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
+ &map_dma, GFP_KERNEL);
- fbi->map_size = info->fix.smem_len;
-
- if (fbi->map_cpu) {
+ if (info->screen_base) {
/* prevent initial garbage on screen */
dprintk("map_video_memory: clear %p:%08x\n",
- fbi->map_cpu, fbi->map_size);
- memset(fbi->map_cpu, 0xf0, fbi->map_size);
+ info->screen_base, map_size);
+ memset(info->screen_base, 0xf0, map_size);
- fbi->screen_dma = fbi->map_dma;
- info->screen_base = fbi->map_cpu;
- info->fix.smem_start = fbi->screen_dma;
+ info->fix.smem_start = map_dma;
- dprintk("map_video_memory: dma=%08x cpu=%p size=%08x\n",
- fbi->map_dma, fbi->map_cpu, info->fix.smem_len);
+ dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
+ info->fix.smem_start, info->screen_base, map_size);
}
- return fbi->map_cpu ? 0 : -ENOMEM;
+ return info->screen_base ? 0 : -ENOMEM;
}
-static inline void s3c2410fb_unmap_video_memory(struct s3c2410fb_info *fbi)
+static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
{
- dma_free_writecombine(fbi->dev, fbi->map_size, fbi->map_cpu,
- fbi->map_dma);
+ struct s3c2410fb_info *fbi = info->par;
+
+ dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
+ info->screen_base, info->fix.smem_start);
}
static inline void modify_gpio(void __iomem *reg,
static int s3c2410fb_init_registers(struct fb_info *info)
{
struct s3c2410fb_info *fbi = info->par;
+ struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
unsigned long flags;
void __iomem *regs = fbi->io;
local_irq_restore(flags);
- writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
- writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
- writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
- writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
- writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
-
- s3c2410fb_set_lcdaddr(info);
-
dprintk("LPCSEL = 0x%08lx\n", mach_info->lpcsel);
writel(mach_info->lpcsel, regs + S3C2410_LPCSEL);
/* ensure temporary palette disabled */
writel(0x00, regs + S3C2410_TPAL);
- /* Enable video by setting the ENVID bit to 1 */
- fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
- writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
return 0;
}
struct s3c2410fb_info *info;
struct s3c2410fb_display *display;
struct fb_info *fbinfo;
+ struct s3c2410fb_mach_info *mach_info;
struct resource *res;
int ret;
int irq;
if (!fbinfo)
return -ENOMEM;
+ platform_set_drvdata(pdev, fbinfo);
+
info = fbinfo->par;
info->dev = &pdev->dev;
goto release_mem;
}
- platform_set_drvdata(pdev, fbinfo);
-
dprintk("devinit\n");
strcpy(fbinfo->fix.id, driver_name);
- info->regs.lcdcon1 = display->lcdcon1;
- info->regs.lcdcon2 = display->lcdcon2;
- info->regs.lcdcon4 = display->lcdcon4;
- info->regs.lcdcon5 = display->lcdcon5;
-
- /* Stop the video and unset ENVID if set */
- info->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
+ /* Stop the video */
lcdcon1 = readl(info->io + S3C2410_LCDCON1);
writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
- info->mach_info = pdev->dev.platform_data;
- info->current_display = mach_info->default_display;
-
fbinfo->fix.type = FB_TYPE_PACKED_PIXELS;
fbinfo->fix.type_aux = 0;
fbinfo->fix.xpanstep = 0;
fbinfo->var.nonstd = 0;
fbinfo->var.activate = FB_ACTIVATE_NOW;
- fbinfo->var.height = display->height;
- fbinfo->var.width = display->width;
fbinfo->var.accel_flags = 0;
fbinfo->var.vmode = FB_VMODE_NONINTERLACED;
fbinfo->flags = FBINFO_FLAG_DEFAULT;
fbinfo->pseudo_palette = &info->pseudo_pal;
- fbinfo->var.xres = display->xres;
- fbinfo->var.xres_virtual = display->xres;
- fbinfo->var.yres = display->yres;
- fbinfo->var.yres_virtual = display->yres;
- fbinfo->var.bits_per_pixel = display->bpp;
- fbinfo->var.left_margin = display->left_margin;
- fbinfo->var.right_margin = display->right_margin;
-
- fbinfo->var.upper_margin =
- S3C2410_LCDCON2_GET_VBPD(display->lcdcon2) + 1;
- fbinfo->var.lower_margin =
- S3C2410_LCDCON2_GET_VFPD(display->lcdcon2) + 1;
- fbinfo->var.vsync_len =
- S3C2410_LCDCON2_GET_VSPW(display->lcdcon2) + 1;
-
- fbinfo->var.hsync_len =
- S3C2410_LCDCON4_GET_HSPW(display->lcdcon4) + 1;
-
- fbinfo->var.red.offset = 11;
- fbinfo->var.green.offset = 5;
- fbinfo->var.blue.offset = 0;
- fbinfo->var.transp.offset = 0;
- fbinfo->var.red.length = 5;
- fbinfo->var.green.length = 6;
- fbinfo->var.blue.length = 5;
- fbinfo->var.transp.length = 0;
-
- /* find maximum required memory size for display */
- for (i = 0; i < mach_info->num_displays; i++) {
- unsigned long smem_len = mach_info->displays[i].xres;
-
- smem_len *= mach_info->displays[i].yres;
- smem_len *= mach_info->displays[i].bpp;
- smem_len >>= 3;
- if (fbinfo->fix.smem_len < smem_len)
- fbinfo->fix.smem_len = smem_len;
- }
-
for (i = 0; i < 256; i++)
info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
msleep(1);
+ /* find maximum required memory size for display */
+ for (i = 0; i < mach_info->num_displays; i++) {
+ unsigned long smem_len = mach_info->displays[i].xres;
+
+ smem_len *= mach_info->displays[i].yres;
+ smem_len *= mach_info->displays[i].bpp;
+ smem_len >>= 3;
+ if (fbinfo->fix.smem_len < smem_len)
+ fbinfo->fix.smem_len = smem_len;
+ }
+
/* Initialize video memory */
ret = s3c2410fb_map_video_memory(fbinfo);
if (ret) {
dprintk("got video memory\n");
+ fbinfo->var.xres = display->xres;
+ fbinfo->var.yres = display->yres;
+ fbinfo->var.bits_per_pixel = display->bpp;
+
s3c2410fb_init_registers(fbinfo);
s3c2410fb_check_var(&fbinfo->var, fbinfo);
return 0;
free_video_memory:
- s3c2410fb_unmap_video_memory(info);
+ s3c2410fb_unmap_video_memory(fbinfo);
release_clock:
clk_disable(info->clk);
clk_put(info->clk);
release_resource(info->mem);
kfree(info->mem);
dealloc_fb:
+ platform_set_drvdata(pdev, NULL);
framebuffer_release(fbinfo);
return ret;
}
struct s3c2410fb_info *info = fbinfo->par;
int irq;
+ unregister_framebuffer(fbinfo);
+
s3c2410fb_stop_lcd(info);
msleep(1);
- s3c2410fb_unmap_video_memory(info);
+ s3c2410fb_unmap_video_memory(fbinfo);
if (info->clk) {
clk_disable(info->clk);
irq = platform_get_irq(pdev, 0);
free_irq(irq, info);
+ iounmap(info->io);
+
release_resource(info->mem);
kfree(info->mem);
- iounmap(info->io);
- unregister_framebuffer(fbinfo);
+
+ platform_set_drvdata(pdev, NULL);
+ framebuffer_release(fbinfo);
return 0;
}
clk_enable(info->clk);
msleep(1);
- s3c2410fb_init_registers(info);
+ s3c2410fb_init_registers(fbinfo);
return 0;
}
},
};
-int __devinit s3c2410fb_init(void)
+int __init s3c2410fb_init(void)
{
return platform_driver_register(&s3c2410fb_driver);
}