#include <linux/fb.h>
+#define GP_REG_COUNT (0x7c / 4)
+#define DC_REG_COUNT (0xf0 / 4)
+#define VP_REG_COUNT (0x158 / 8)
+#define FP_REG_COUNT (0x60 / 8)
+
+#define DC_PAL_COUNT 0x104
+#define DC_HFILT_COUNT 0x100
+#define DC_VFILT_COUNT 0x100
+#define VP_COEFF_SIZE 0x1000
+
#define OUTPUT_CRT 0x01
#define OUTPUT_PANEL 0x02
struct lxfb_par {
int output;
- int panel_width;
- int panel_height;
void __iomem *gp_regs;
void __iomem *dc_regs;
- void __iomem *df_regs;
+ void __iomem *vp_regs;
+#ifdef CONFIG_PM
+ int powered_down;
+
+ /* register state, for power mgmt functionality */
+ struct {
+ uint64_t padsel;
+ uint64_t dotpll;
+ uint64_t dfglcfg;
+ uint64_t dcspare;
+ } msr;
+
+ uint32_t gp[GP_REG_COUNT];
+ uint32_t dc[DC_REG_COUNT];
+ uint64_t vp[VP_REG_COUNT];
+ uint64_t fp[FP_REG_COUNT];
+
+ uint32_t pal[DC_PAL_COUNT];
+ uint32_t hcoeff[DC_HFILT_COUNT * 2];
+ uint32_t vcoeff[DC_VFILT_COUNT];
+ uint32_t vp_coeff[VP_COEFF_SIZE / 4];
+#endif
};
static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
unsigned int, unsigned int);
-/* MSRS */
-
-#define GLCP_DOTPLL_RESET (1 << 0)
-#define GLCP_DOTPLL_BYPASS (1 << 15)
-#define GLCP_DOTPLL_HALFPIX (1 << 24)
-#define GLCP_DOTPLL_LOCK (1 << 25)
-
-#define DF_CONFIG_OUTPUT_MASK 0x38
-#define DF_OUTPUT_PANEL 0x08
-#define DF_OUTPUT_CRT 0x00
-#define DF_SIMULTANEOUS_CRT_AND_FP (1 << 15)
-
-#define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF
-#define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F
-
-#define DC_SPARE_DISABLE_CFIFO_HGO 0x00000800
-#define DC_SPARE_VFIFO_ARB_SELECT 0x00000400
-#define DC_SPARE_WM_LPEN_OVRD 0x00000200
-#define DC_SPARE_LOAD_WM_LPEN_MASK 0x00000100
-#define DC_SPARE_DISABLE_INIT_VID_PRI 0x00000080
-#define DC_SPARE_DISABLE_VFIFO_WM 0x00000040
-#define DC_SPARE_DISABLE_CWD_CHECK 0x00000020
-#define DC_SPARE_PIX8_PAN_FIX 0x00000010
-#define DC_SPARE_FIRST_REQ_MASK 0x00000002
+#ifdef CONFIG_PM
+int lx_powerdown(struct fb_info *info);
+int lx_powerup(struct fb_info *info);
+#endif
/* Graphics Processor registers (table 6-29 from the data book) */
#define DC_DV_CTL_DV_LINE_SIZE_2K (1 << 10)
#define DC_DV_CTL_DV_LINE_SIZE_4K (1 << 11)
#define DC_DV_CTL_DV_LINE_SIZE_8K ((1 << 10) | (1 << 11))
+#define DC_DV_CTL_CLEAR_DV_RAM (1 << 0)
+
+#define DC_IRQ_FILT_CTL_H_FILT_SEL (1 << 10)
#define DC_CLR_KEY_CLR_KEY_EN (1 << 24)
VP_A2YE,
VP_A3YE, /* 0x150 */
+
+ VP_VCR = 0x1000, /* 0x1000 - 0x1fff */
};
#define VP_VCFG_VID_EN (1 << 0)
#define FP_PT2_SCRC (1 << 27) /* shfclk free */
#define FP_PM_P (1 << 24) /* panel power ctl */
+#define FP_PM_PANEL_PWR_UP (1 << 3) /* r/o */
+#define FP_PM_PANEL_PWR_DOWN (1 << 2) /* r/o */
+#define FP_PM_PANEL_OFF (1 << 1) /* r/o */
+#define FP_PM_PANEL_ON (1 << 0) /* r/o */
#define FP_DFC_BC ((1 << 4) | (1 << 5) | (1 << 6))
static inline uint32_t read_vp(struct lxfb_par *par, int reg)
{
- return readl(par->df_regs + 8*reg);
+ return readl(par->vp_regs + 8*reg);
}
static inline void write_vp(struct lxfb_par *par, int reg, uint32_t val)
{
- writel(val, par->df_regs + 8*reg);
+ writel(val, par->vp_regs + 8*reg);
}
static inline uint32_t read_fp(struct lxfb_par *par, int reg)
{
- return readl(par->df_regs + 8*reg + VP_FP_START);
+ return readl(par->vp_regs + 8*reg + VP_FP_START);
}
static inline void write_fp(struct lxfb_par *par, int reg, uint32_t val)
{
- writel(val, par->df_regs + 8*reg + VP_FP_START);
+ writel(val, par->vp_regs + 8*reg + VP_FP_START);
}
+
+/* MSRs are defined in asm/geode.h; their bitfields are here */
+
+#define MSR_GLCP_DOTPLL_LOCK (1 << 25) /* r/o */
+#define MSR_GLCP_DOTPLL_HALFPIX (1 << 24)
+#define MSR_GLCP_DOTPLL_BYPASS (1 << 15)
+#define MSR_GLCP_DOTPLL_DOTRESET (1 << 0)
+
+/* note: this is actually the VP's GLD_MSR_CONFIG */
+#define MSR_LX_GLD_MSR_CONFIG_FMT ((1 << 3) | (1 << 4) | (1 << 5))
+#define MSR_LX_GLD_MSR_CONFIG_FMT_FP (1 << 3)
+#define MSR_LX_GLD_MSR_CONFIG_FMT_CRT (0)
+#define MSR_LX_GLD_MSR_CONFIG_FPC (1 << 15) /* FP *and* CRT */
+
+#define MSR_LX_MSR_PADSEL_TFT_SEL_LOW 0xDFFFFFFF /* ??? */
+#define MSR_LX_MSR_PADSEL_TFT_SEL_HIGH 0x0000003F /* ??? */
+
+#define MSR_LX_SPARE_MSR_DIS_CFIFO_HGO (1 << 11) /* undocumented */
+#define MSR_LX_SPARE_MSR_VFIFO_ARB_SEL (1 << 10) /* undocumented */
+#define MSR_LX_SPARE_MSR_WM_LPEN_OVRD (1 << 9) /* undocumented */
+#define MSR_LX_SPARE_MSR_LOAD_WM_LPEN_M (1 << 8) /* undocumented */
+#define MSR_LX_SPARE_MSR_DIS_INIT_V_PRI (1 << 7) /* undocumented */
+#define MSR_LX_SPARE_MSR_DIS_VIFO_WM (1 << 6)
+#define MSR_LX_SPARE_MSR_DIS_CWD_CHECK (1 << 5) /* undocumented */
+#define MSR_LX_SPARE_MSR_PIX8_PAN_FIX (1 << 4) /* undocumented */
+#define MSR_LX_SPARE_MSR_FIRST_REQ_MASK (1 << 1) /* undocumented */
+
#endif
projects / linux-2.6 / blobdiff