/* PCMCIA configuration registers */
-#define SSB_PCMCIA_CORECTL 0x00
-#define SSB_PCMCIA_CORECTL_RESET 0x80 /* Core reset */
-#define SSB_PCMCIA_CORECTL_IRQEN 0x04 /* IRQ enable */
-#define SSB_PCMCIA_CORECTL_FUNCEN 0x01 /* Function enable */
-#define SSB_PCMCIA_CORECTL2 0x80
#define SSB_PCMCIA_ADDRESS0 0x2E
#define SSB_PCMCIA_ADDRESS1 0x30
#define SSB_PCMCIA_ADDRESS2 0x32
return (lo | (hi << 16));
}
+#ifdef CONFIG_SSB_BLOCKIO
+static void ssb_pcmcia_block_read(struct ssb_device *dev, void *buffer,
+ size_t count, u16 offset, u8 reg_width)
+{
+ struct ssb_bus *bus = dev->bus;
+ unsigned long flags;
+ void __iomem *addr = bus->mmio + offset;
+ int err;
+
+ spin_lock_irqsave(&bus->bar_lock, flags);
+ err = select_core_and_segment(dev, &offset);
+ if (unlikely(err)) {
+ memset(buffer, 0xFF, count);
+ goto unlock;
+ }
+ switch (reg_width) {
+ case sizeof(u8): {
+ u8 *buf = buffer;
+
+ while (count) {
+ *buf = __raw_readb(addr);
+ buf++;
+ count--;
+ }
+ break;
+ }
+ case sizeof(u16): {
+ __le16 *buf = buffer;
+
+ SSB_WARN_ON(count & 1);
+ while (count) {
+ *buf = (__force __le16)__raw_readw(addr);
+ buf++;
+ count -= 2;
+ }
+ break;
+ }
+ case sizeof(u32): {
+ __le16 *buf = buffer;
+
+ SSB_WARN_ON(count & 3);
+ while (count) {
+ *buf = (__force __le16)__raw_readw(addr);
+ buf++;
+ *buf = (__force __le16)__raw_readw(addr + 2);
+ buf++;
+ count -= 4;
+ }
+ break;
+ }
+ default:
+ SSB_WARN_ON(1);
+ }
+unlock:
+ spin_unlock_irqrestore(&bus->bar_lock, flags);
+}
+#endif /* CONFIG_SSB_BLOCKIO */
+
static void ssb_pcmcia_write8(struct ssb_device *dev, u16 offset, u8 value)
{
struct ssb_bus *bus = dev->bus;
spin_unlock_irqrestore(&bus->bar_lock, flags);
}
+#ifdef CONFIG_SSB_BLOCKIO
+static void ssb_pcmcia_block_write(struct ssb_device *dev, const void *buffer,
+ size_t count, u16 offset, u8 reg_width)
+{
+ struct ssb_bus *bus = dev->bus;
+ unsigned long flags;
+ void __iomem *addr = bus->mmio + offset;
+ int err;
+
+ spin_lock_irqsave(&bus->bar_lock, flags);
+ err = select_core_and_segment(dev, &offset);
+ if (unlikely(err))
+ goto unlock;
+ switch (reg_width) {
+ case sizeof(u8): {
+ const u8 *buf = buffer;
+
+ while (count) {
+ __raw_writeb(*buf, addr);
+ buf++;
+ count--;
+ }
+ break;
+ }
+ case sizeof(u16): {
+ const __le16 *buf = buffer;
+
+ SSB_WARN_ON(count & 1);
+ while (count) {
+ __raw_writew((__force u16)(*buf), addr);
+ buf++;
+ count -= 2;
+ }
+ break;
+ }
+ case sizeof(u32): {
+ const __le16 *buf = buffer;
+
+ SSB_WARN_ON(count & 3);
+ while (count) {
+ __raw_writew((__force u16)(*buf), addr);
+ buf++;
+ __raw_writew((__force u16)(*buf), addr + 2);
+ buf++;
+ count -= 4;
+ }
+ break;
+ }
+ default:
+ SSB_WARN_ON(1);
+ }
+unlock:
+ mmiowb();
+ spin_unlock_irqrestore(&bus->bar_lock, flags);
+}
+#endif /* CONFIG_SSB_BLOCKIO */
+
/* Not "static", as it's used in main.c */
const struct ssb_bus_ops ssb_pcmcia_ops = {
.read8 = ssb_pcmcia_read8,
.write8 = ssb_pcmcia_write8,
.write16 = ssb_pcmcia_write16,
.write32 = ssb_pcmcia_write32,
+#ifdef CONFIG_SSB_BLOCKIO
+ .block_read = ssb_pcmcia_block_read,
+ .block_write = ssb_pcmcia_block_write,
+#endif
};
static int ssb_pcmcia_sprom_command(struct ssb_bus *bus, u8 command)
ssb_pcmcia_attr_sprom_show,
ssb_pcmcia_attr_sprom_store);
+static int ssb_pcmcia_cor_setup(struct ssb_bus *bus, u8 cor)
+{
+ u8 val;
+ int err;
+
+ err = ssb_pcmcia_cfg_read(bus, cor, &val);
+ if (err)
+ return err;
+ val &= ~COR_SOFT_RESET;
+ val |= COR_FUNC_ENA | COR_IREQ_ENA | COR_LEVEL_REQ;
+ err = ssb_pcmcia_cfg_write(bus, cor, val);
+ if (err)
+ return err;
+ msleep(40);
+
+ return 0;
+}
+
+/* Initialize the PCMCIA hardware. This is called on Init and Resume. */
+int ssb_pcmcia_hardware_setup(struct ssb_bus *bus)
+{
+ int err;
+
+ if (bus->bustype != SSB_BUSTYPE_PCMCIA)
+ return 0;
+
+ /* Switch segment to a known state and sync
+ * bus->mapped_pcmcia_seg with hardware state. */
+ ssb_pcmcia_switch_segment(bus, 0);
+ /* Init the COR register. */
+ err = ssb_pcmcia_cor_setup(bus, CISREG_COR);
+ if (err)
+ return err;
+ /* Some cards also need this register to get poked. */
+ err = ssb_pcmcia_cor_setup(bus, CISREG_COR + 0x80);
+ if (err)
+ return err;
+
+ return 0;
+}
+
void ssb_pcmcia_exit(struct ssb_bus *bus)
{
if (bus->bustype != SSB_BUSTYPE_PCMCIA)
int ssb_pcmcia_init(struct ssb_bus *bus)
{
- u8 val, offset;
int err;
if (bus->bustype != SSB_BUSTYPE_PCMCIA)
return 0;
- /* Switch segment to a known state and sync
- * bus->mapped_pcmcia_seg with hardware state. */
- ssb_pcmcia_switch_segment(bus, 0);
-
- /* Init IRQ routing */
- if (bus->chip_id == 0x4306)
- offset = SSB_PCMCIA_CORECTL;
- else
- offset = SSB_PCMCIA_CORECTL2;
- err = ssb_pcmcia_cfg_read(bus, offset, &val);
- if (err)
- goto error;
- val |= SSB_PCMCIA_CORECTL_IRQEN | SSB_PCMCIA_CORECTL_FUNCEN;
- err = ssb_pcmcia_cfg_write(bus, offset, val);
+ err = ssb_pcmcia_hardware_setup(bus);
if (err)
goto error;