* 4) AFAICT, hardware flow control isn't supported by the controller --MAG.
*/
+#include <linux/platform_device.h>
+
#include "mpsc.h"
/*
static struct mpsc_port_info mpsc_ports[MPSC_NUM_CTLRS];
static struct mpsc_shared_regs mpsc_shared_regs;
+static struct uart_driver mpsc_reg;
+static void mpsc_start_rx(struct mpsc_port_info *pi);
+static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
+static void mpsc_release_port(struct uart_port *port);
/*
******************************************************************************
*
mpsc_sdma_cmd(pi, SDMA_SDCM_AR | SDMA_SDCM_AT);
/* Clear the SDMA current and first TX and RX pointers */
- mpsc_sdma_set_tx_ring(pi, 0);
- mpsc_sdma_set_rx_ring(pi, 0);
+ mpsc_sdma_set_tx_ring(pi, NULL);
+ mpsc_sdma_set_rx_ring(pi, NULL);
/* Disable interrupts */
mpsc_sdma_intr_mask(pi, 0xf);
mpsc_alloc_ring_mem(struct mpsc_port_info *pi)
{
int rc = 0;
- static void mpsc_free_ring_mem(struct mpsc_port_info *pi);
pr_debug("mpsc_alloc_ring_mem[%d]: Allocating ring mem\n",
pi->port.line);
int rc = 0;
u8 *bp;
char flag = TTY_NORMAL;
- static void mpsc_start_rx(struct mpsc_port_info *pi);
pr_debug("mpsc_rx_intr[%d]: Handling Rx intr\n", pi->port.line);
{
struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
u32 mflags, status;
- ulong iflags;
- spin_lock_irqsave(&pi->port.lock, iflags);
status = (pi->mirror_regs) ? pi->MPSC_CHR_10_m :
readl(pi->mpsc_base + MPSC_CHR_10);
- spin_unlock_irqrestore(&pi->port.lock, iflags);
mflags = 0;
if (status & 0x1)
}
static void
-mpsc_stop_tx(struct uart_port *port, uint tty_start)
+mpsc_stop_tx(struct uart_port *port)
{
struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
- pr_debug("mpsc_stop_tx[%d]: tty_start: %d\n", port->line, tty_start);
+ pr_debug("mpsc_stop_tx[%d]\n", port->line);
mpsc_freeze(pi);
return;
}
static void
-mpsc_start_tx(struct uart_port *port, uint tty_start)
+mpsc_start_tx(struct uart_port *port)
{
struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
mpsc_copy_tx_data(pi);
mpsc_sdma_start_tx(pi);
- pr_debug("mpsc_start_tx[%d]: tty_start: %d\n", port->line, tty_start);
+ pr_debug("mpsc_start_tx[%d]\n", port->line);
return;
}
{
pr_debug("mpsc_start_rx[%d]: Starting...\n", pi->port.line);
+ /* Issue a Receive Abort to clear any receive errors */
+ writel(MPSC_CHR_2_RA, pi->mpsc_base + MPSC_CHR_2);
if (pi->rcv_data) {
mpsc_enter_hunt(pi);
mpsc_sdma_cmd(pi, SDMA_SDCM_ERD);
mpsc_shutdown(struct uart_port *port)
{
struct mpsc_port_info *pi = (struct mpsc_port_info *)port;
- static void mpsc_release_port(struct uart_port *port);
pr_debug("mpsc_shutdown[%d]: Shutting down MPSC\n", port->line);
return uart_set_options(&pi->port, co, baud, parity, bits, flow);
}
-extern struct uart_driver mpsc_reg;
static struct console mpsc_console = {
.name = MPSC_DEV_NAME,
.write = mpsc_console_write,
MPSC_SDMA_INTR_REG_BLOCK_SIZE);
}
- mpsc_shared_regs.mpsc_routing_base = 0;
- mpsc_shared_regs.sdma_intr_base = 0;
+ mpsc_shared_regs.mpsc_routing_base = NULL;
+ mpsc_shared_regs.sdma_intr_base = NULL;
mpsc_shared_regs.mpsc_routing_base_p = 0;
mpsc_shared_regs.sdma_intr_base_p = 0;
release_mem_region(pi->brg_base_p, MPSC_BRG_REG_BLOCK_SIZE);
}
- pi->mpsc_base = 0;
- pi->sdma_base = 0;
- pi->brg_base = 0;
+ pi->mpsc_base = NULL;
+ pi->sdma_base = NULL;
+ pi->brg_base = NULL;
pi->mpsc_base_p = 0;
pi->sdma_base_p = 0;