handled += ata_host_intr(ap, qc);
} else if (is_vsc_sata_int_err(i, int_status)) {
/*
- * On some chips (i.e. Intel 31244), an error
+ * On some chips (i.e. Intel 31244), an error
* interrupt will sneak in at initialization
* time (phy state changes). Clearing the SCR
* error register is not required, but it prevents
- * the phy state change interrupts from recurring
+ * the phy state change interrupts from recurring
* later.
*/
u32 err_status;