#include <linux/spinlock.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
+#include <linux/ctype.h>
#include <scsi/libsas.h>
#include <asm/io.h>
#define DRV_NAME "mvsas"
-#define DRV_VERSION "0.5"
+#define DRV_VERSION "0.5.1"
#define _MV_DUMP 0
#define MVS_DISABLE_NVRAM
#define MVS_DISABLE_MSI
void *funcdata);
static u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port);
static void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val);
-static u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port);
-static void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
- u32 port, u32 val);
-static u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port);
-static void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val);
-static void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr);
-static u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port);
-static void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val);
-static void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr);
static u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port);
static void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val);
static void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val);
static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i);
static void mvs_detect_porttype(struct mvs_info *mvi, int i);
static void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
-static void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port);
-static u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port);
-static u32 mvs_is_sig_fis_received(u32 irq_status);
static int mvs_scan_finished(struct Scsi_Host *, unsigned long);
static void mvs_scan_start(struct Scsi_Host *);
return rc;
#else
/* FIXME , For SAS target mode */
- memcpy(buf, "\x00\x00\xab\x11\x30\x04\x05\x50", 8);
+ memcpy(buf, "\x50\x05\x04\x30\x11\xab\x00\x00", 8);
return 0;
#endif
}
mvs_hba_cq_dump(mvi);
- if (unlikely(rx_desc & RXQ_DONE))
+ if (likely(rx_desc & RXQ_DONE))
mvs_slot_complete(mvi, rx_desc);
if (rx_desc & RXQ_ATTN) {
attn = true;
msleep(100);
/* init and reset phys */
for (i = 0; i < mvi->chip->n_phy; i++) {
- /* FIXME: is this the correct dword order? */
- u32 lo = *((u32 *)&mvi->sas_addr[0]);
- u32 hi = *((u32 *)&mvi->sas_addr[4]);
+ u32 lo = be32_to_cpu(*(u32 *)&mvi->sas_addr[4]);
+ u32 hi = be32_to_cpu(*(u32 *)&mvi->sas_addr[0]);
mvs_detect_porttype(mvi, i);