* reading the dword at 0x100 which must either be 0 or a valid extended
* capability header.
*/
+int pci_cfg_space_size_ext(struct pci_dev *dev)
+{
+ u32 status;
+
+ if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
+ goto fail;
+ if (status == 0xffffffff)
+ goto fail;
+
+ return PCI_CFG_SPACE_EXP_SIZE;
+
+ fail:
+ return PCI_CFG_SPACE_SIZE;
+}
+
int pci_cfg_space_size(struct pci_dev *dev)
{
int pos;
goto fail;
}
- if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
- goto fail;
- if (status == 0xffffffff)
- goto fail;
-
- return PCI_CFG_SPACE_EXP_SIZE;
+ return pci_cfg_space_size_ext(dev);
fail:
return PCI_CFG_SPACE_SIZE;
dev->dev.release = pci_release_dev;
pci_dev_get(dev);
- set_dev_node(&dev->dev, pcibus_to_node(bus));
dev->dev.dma_mask = &dev->dma_mask;
dev->dev.dma_parms = &dev->dma_parms;
dev->dev.coherent_dma_mask = 0xffffffffull;
return max;
}
+void __attribute__((weak)) set_pci_bus_resources_arch_default(struct pci_bus *b)
+{
+}
+
struct pci_bus * pci_create_bus(struct device *parent,
int bus, struct pci_ops *ops, void *sysdata)
{
goto dev_reg_err;
b->bridge = get_device(dev);
+ if (!parent)
+ set_dev_node(b->bridge, pcibus_to_node(b));
+
b->dev.class = &pcibus_class;
b->dev.parent = b->bridge;
sprintf(b->dev.bus_id, "%04x:%02x", pci_domain_nr(b), bus);
b->resource[0] = &ioport_resource;
b->resource[1] = &iomem_resource;
+ set_pci_bus_resources_arch_default(b);
+
return b;
dev_create_file_err: