#define MRLSENSOR 0x40000000
#define ATTN_BUTTON 0x80000000
+/*
+ * Interrupt Locator Register definitions
+ */
+#define CMD_INTR_PENDING (1 << 0)
+#define SLOT_INTR_PENDING(i) (1 << (i + 1))
+
/*
* Controller SERR-INT Register
*/
#define CON_PFAULT_SERR_MASK (1 << 30)
#define SLOT_REG_RSVDZ_MASK (1 << 15) | (7 << 21)
-/* SHPC 'write' operations/commands */
-
-/* Slot operation - 0x00h to 0x3Fh */
-
-#define NO_CHANGE 0x00
-
-/* Slot state - Bits 0 & 1 of controller command register */
-#define SET_SLOT_PWR 0x01
-#define SET_SLOT_ENABLE 0x02
-#define SET_SLOT_DISABLE 0x03
-
-/* Power indicator state - Bits 2 & 3 of controller command register*/
-#define SET_PWR_ON 0x04
-#define SET_PWR_BLINK 0x08
-#define SET_PWR_OFF 0x0C
-
-/* Attention indicator state - Bits 4 & 5 of controller command register*/
-#define SET_ATTN_ON 0x010
-#define SET_ATTN_BLINK 0x020
-#define SET_ATTN_OFF 0x030
-
-/* Set bus speed/mode A - 0x40h to 0x47h */
-#define SETA_PCI_33MHZ 0x40
+/*
+ * SHPC Command Code definitnions
+ *
+ * Slot Operation 00h - 3Fh
+ * Set Bus Segment Speed/Mode A 40h - 47h
+ * Power-Only All Slots 48h
+ * Enable All Slots 49h
+ * Set Bus Segment Speed/Mode B (PI=2) 50h - 5Fh
+ * Reserved Command Codes 60h - BFh
+ * Vendor Specific Commands C0h - FFh
+ */
+#define SET_SLOT_PWR 0x01 /* Slot Operation */
+#define SET_SLOT_ENABLE 0x02
+#define SET_SLOT_DISABLE 0x03
+#define SET_PWR_ON 0x04
+#define SET_PWR_BLINK 0x08
+#define SET_PWR_OFF 0x0c
+#define SET_ATTN_ON 0x10
+#define SET_ATTN_BLINK 0x20
+#define SET_ATTN_OFF 0x30
+#define SETA_PCI_33MHZ 0x40 /* Set Bus Segment Speed/Mode A */
#define SETA_PCI_66MHZ 0x41
#define SETA_PCIX_66MHZ 0x42
#define SETA_PCIX_100MHZ 0x43
#define SETA_PCIX_133MHZ 0x44
-#define RESERV_1 0x45
-#define RESERV_2 0x46
-#define RESERV_3 0x47
-
-/* Set bus speed/mode B - 0x50h to 0x5fh */
-#define SETB_PCI_33MHZ 0x50
+#define SETA_RESERVED1 0x45
+#define SETA_RESERVED2 0x46
+#define SETA_RESERVED3 0x47
+#define SET_PWR_ONLY_ALL 0x48 /* Power-Only All Slots */
+#define SET_ENABLE_ALL 0x49 /* Enable All Slots */
+#define SETB_PCI_33MHZ 0x50 /* Set Bus Segment Speed/Mode B */
#define SETB_PCI_66MHZ 0x51
#define SETB_PCIX_66MHZ_PM 0x52
#define SETB_PCIX_100MHZ_PM 0x53
#define SETB_PCIX_66MHZ_533 0x5b
#define SETB_PCIX_100MHZ_533 0x5c
#define SETB_PCIX_133MHZ_533 0x5d
+#define SETB_RESERVED1 0x5e
+#define SETB_RESERVED2 0x5f
-
-/* Power-on all slots - 0x48h */
-#define SET_PWR_ON_ALL 0x48
-
-/* Enable all slots - 0x49h */
-#define SET_ENABLE_ALL 0x49
-
-/* SHPC controller command error code */
+/*
+ * SHPC controller command error code
+ */
#define SWITCH_OPEN 0x1
#define INVALID_CMD 0x2
#define INVALID_SPEED_MODE 0x4
-/* For accessing SHPC Working Register Set */
+/*
+ * For accessing SHPC Working Register Set via PCI Configuration Space
+ */
#define DWORD_SELECT 0x2
#define DWORD_DATA 0x4
-#define BASE_OFFSET 0x0
/* Field Offset in Logical Slot Register - byte boundary */
#define SLOT_EVENT_LATCH 0x2
#define SLOT_SERR_INT_MASK 0x3
-static spinlock_t hpc_event_lock;
-
DEFINE_DBG_BUFFER /* Debug string buffer for entire HPC defined here */
static struct php_ctlr_state_s *php_ctlr_list_head; /* HPC state linked list */
static int ctlr_seq_num = 0; /* Controller sequenc # */
static atomic_t shpchp_num_controllers = ATOMIC_INIT(0);
-static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs);
-
-static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds);
+static irqreturn_t shpc_isr(int irq, void *dev_id);
+static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec);
static int hpc_check_cmd_status(struct controller *ctrl);
static inline u8 shpc_readb(struct controller *ctrl, int reg)
return pci_read_config_dword(pdev, cap_offset + DWORD_DATA, value);
}
-/* This is the interrupt polling timeout function. */
+/*
+ * This is the interrupt polling timeout function.
+ */
static void int_poll_timeout(unsigned long lphp_ctlr)
{
- struct php_ctlr_state_s *php_ctlr = (struct php_ctlr_state_s *)lphp_ctlr;
-
- DBG_ENTER_ROUTINE
+ struct php_ctlr_state_s *php_ctlr =
+ (struct php_ctlr_state_s *)lphp_ctlr;
- if ( !php_ctlr ) {
- err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
- return;
- }
+ DBG_ENTER_ROUTINE
- /* Poll for interrupt events. regs == NULL => polling */
- shpc_isr( 0, (void *)php_ctlr, NULL );
+ /* Poll for interrupt events. regs == NULL => polling */
+ shpc_isr(0, php_ctlr->callback_instance_id);
- init_timer(&php_ctlr->int_poll_timer);
+ init_timer(&php_ctlr->int_poll_timer);
if (!shpchp_poll_time)
- shpchp_poll_time = 2; /* reset timer to poll in 2 secs if user doesn't specify at module installation*/
+ shpchp_poll_time = 2; /* default polling interval is 2 sec */
- start_int_poll_timer(php_ctlr, shpchp_poll_time);
-
- return;
+ start_int_poll_timer(php_ctlr, shpchp_poll_time);
+
+ DBG_LEAVE_ROUTINE
+}
+
+/*
+ * This function starts the interrupt polling timer.
+ */
+static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int sec)
+{
+ /* Clamp to sane value */
+ if ((sec <= 0) || (sec > 60))
+ sec = 2;
+
+ php_ctlr->int_poll_timer.function = &int_poll_timeout;
+ php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr;
+ php_ctlr->int_poll_timer.expires = jiffies + sec * HZ;
+ add_timer(&php_ctlr->int_poll_timer);
}
-/* This function starts the interrupt polling timer. */
-static void start_int_poll_timer(struct php_ctlr_state_s *php_ctlr, int seconds)
+static inline int is_ctrl_busy(struct controller *ctrl)
{
- if (!php_ctlr) {
- err("%s: Invalid HPC controller handle!\n", __FUNCTION__);
- return;
- }
+ u16 cmd_status = shpc_readw(ctrl, CMD_STATUS);
+ return cmd_status & 0x1;
+}
+
+/*
+ * Returns 1 if SHPC finishes executing a command within 1 sec,
+ * otherwise returns 0.
+ */
+static inline int shpc_poll_ctrl_busy(struct controller *ctrl)
+{
+ int i;
- if ( ( seconds <= 0 ) || ( seconds > 60 ) )
- seconds = 2; /* Clamp to sane value */
+ if (!is_ctrl_busy(ctrl))
+ return 1;
- php_ctlr->int_poll_timer.function = &int_poll_timeout;
- php_ctlr->int_poll_timer.data = (unsigned long)php_ctlr; /* Instance data */
- php_ctlr->int_poll_timer.expires = jiffies + seconds * HZ;
- add_timer(&php_ctlr->int_poll_timer);
+ /* Check every 0.1 sec for a total of 1 sec */
+ for (i = 0; i < 10; i++) {
+ msleep(100);
+ if (!is_ctrl_busy(ctrl))
+ return 1;
+ }
- return;
+ return 0;
}
static inline int shpc_wait_cmd(struct controller *ctrl)
{
int retval = 0;
- unsigned int timeout_msec = shpchp_poll_mode ? 2000 : 1000;
- unsigned long timeout = msecs_to_jiffies(timeout_msec);
- int rc = wait_event_interruptible_timeout(ctrl->queue,
- !ctrl->cmd_busy, timeout);
- if (!rc) {
+ unsigned long timeout = msecs_to_jiffies(1000);
+ int rc;
+
+ if (shpchp_poll_mode)
+ rc = shpc_poll_ctrl_busy(ctrl);
+ else
+ rc = wait_event_interruptible_timeout(ctrl->queue,
+ !is_ctrl_busy(ctrl), timeout);
+ if (!rc && is_ctrl_busy(ctrl)) {
retval = -EIO;
- err("Command not completed in %d msec\n", timeout_msec);
+ err("Command not completed in 1000 msec\n");
} else if (rc < 0) {
retval = -EINTR;
info("Command was interrupted by a signal\n");
}
- ctrl->cmd_busy = 0;
return retval;
}
u16 cmd_status;
int retval = 0;
u16 temp_word;
- int i;
DBG_ENTER_ROUTINE
mutex_lock(&slot->ctrl->cmd_lock);
- for (i = 0; i < 10; i++) {
- cmd_status = shpc_readw(ctrl, CMD_STATUS);
-
- if (!(cmd_status & 0x1))
- break;
- /* Check every 0.1 sec for a total of 1 sec*/
- msleep(100);
- }
-
- cmd_status = shpc_readw(ctrl, CMD_STATUS);
-
- if (cmd_status & 0x1) {
+ if (!shpc_poll_ctrl_busy(ctrl)) {
/* After 1 sec and and the controller is still busy */
- err("%s : Controller is still busy after 1 sec.\n", __FUNCTION__);
+ err("%s : Controller is still busy after 1 sec.\n",
+ __FUNCTION__);
retval = -EBUSY;
goto out;
}
/* To make sure the Controller Busy bit is 0 before we send out the
* command.
*/
- slot->ctrl->cmd_busy = 1;
shpc_writew(ctrl, CMD, temp_word);
/*
switch (value) {
case 0 :
- slot_cmd = 0x30; /* OFF */
+ slot_cmd = SET_ATTN_OFF; /* OFF */
break;
case 1:
- slot_cmd = 0x10; /* ON */
+ slot_cmd = SET_ATTN_ON; /* ON */
break;
case 2:
- slot_cmd = 0x20; /* BLINK */
+ slot_cmd = SET_ATTN_BLINK; /* BLINK */
break;
default:
return -1;
static void hpc_set_green_led_on(struct slot *slot)
{
- shpc_write_cmd(slot, slot->hp_slot, 0x04);
+ shpc_write_cmd(slot, slot->hp_slot, SET_PWR_ON);
}
static void hpc_set_green_led_off(struct slot *slot)
{
- shpc_write_cmd(slot, slot->hp_slot, 0x0c);
+ shpc_write_cmd(slot, slot->hp_slot, SET_PWR_OFF);
}
static void hpc_set_green_led_blink(struct slot *slot)
{
- shpc_write_cmd(slot, slot->hp_slot, 0x08);
+ shpc_write_cmd(slot, slot->hp_slot, SET_PWR_BLINK);
}
int shpc_get_ctlr_slot_config(struct controller *ctrl,
DBG_ENTER_ROUTINE
- retval = shpc_write_cmd(slot, slot->hp_slot, 0x01);
+ retval = shpc_write_cmd(slot, slot->hp_slot, SET_SLOT_PWR);
if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
return retval;
DBG_ENTER_ROUTINE
- /* 3A => Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
- retval = shpc_write_cmd(slot, slot->hp_slot, 0x3a);
+ /* Slot - Enable, Power Indicator - Blink, Attention Indicator - Off */
+ retval = shpc_write_cmd(slot, slot->hp_slot,
+ SET_SLOT_ENABLE | SET_PWR_BLINK | SET_ATTN_OFF);
if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
return retval;
DBG_ENTER_ROUTINE
- /* 1F => Slot - Disable, Power Indicator - Off, Attention Indicator - On */
- retval = shpc_write_cmd(slot, slot->hp_slot, 0x1f);
+ /* Slot - Disable, Power Indicator - Off, Attention Indicator - On */
+ retval = shpc_write_cmd(slot, slot->hp_slot,
+ SET_SLOT_DISABLE | SET_PWR_OFF | SET_ATTN_ON);
if (retval) {
err("%s: Write command failed!\n", __FUNCTION__);
return retval;
return retval;
}
-static irqreturn_t shpc_isr(int IRQ, void *dev_id, struct pt_regs *regs)
+static irqreturn_t shpc_isr(int irq, void *dev_id)
{
- struct controller *ctrl = NULL;
- struct php_ctlr_state_s *php_ctlr;
- u8 schedule_flag = 0;
- u32 temp_dword, intr_loc, intr_loc2;
+ struct controller *ctrl = (struct controller *)dev_id;
+ struct php_ctlr_state_s *php_ctlr = ctrl->hpc_ctlr_handle;
+ u32 serr_int, slot_reg, intr_loc, intr_loc2;
int hp_slot;
- if (!dev_id)
- return IRQ_NONE;
-
- if (!shpchp_poll_mode) {
- ctrl = (struct controller *)dev_id;
- php_ctlr = ctrl->hpc_ctlr_handle;
- } else {
- php_ctlr = (struct php_ctlr_state_s *) dev_id;
- ctrl = (struct controller *)php_ctlr->callback_instance_id;
- }
-
- if (!ctrl)
- return IRQ_NONE;
-
- if (!php_ctlr || !php_ctlr->creg)
- return IRQ_NONE;
-
/* Check to see if it was our interrupt */
intr_loc = shpc_readl(ctrl, INTR_LOC);
-
if (!intr_loc)
return IRQ_NONE;
+
dbg("%s: intr_loc = %x\n",__FUNCTION__, intr_loc);
if(!shpchp_poll_mode) {
- /* Mask Global Interrupt Mask - see implementation note on p. 139 */
- /* of SHPC spec rev 1.0*/
- temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- temp_dword |= GLOBAL_INTR_MASK;
- temp_dword &= ~SERR_INTR_RSVDZ_MASK;
- shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
+ /*
+ * Mask Global Interrupt Mask - see implementation
+ * note on p. 139 of SHPC spec rev 1.0
+ */
+ serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
+ serr_int |= GLOBAL_INTR_MASK;
+ serr_int &= ~SERR_INTR_RSVDZ_MASK;
+ shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
intr_loc2 = shpc_readl(ctrl, INTR_LOC);
dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
}
- if (intr_loc & 0x0001) {
+ if (intr_loc & CMD_INTR_PENDING) {
/*
* Command Complete Interrupt Pending
* RO only - clear by writing 1 to the Command Completion
* Detect bit in Controller SERR-INT register
*/
- temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- temp_dword &= ~SERR_INTR_RSVDZ_MASK;
- shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
- ctrl->cmd_busy = 0;
+ serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
+ serr_int &= ~SERR_INTR_RSVDZ_MASK;
+ shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
+
wake_up_interruptible(&ctrl->queue);
}
- if ((intr_loc = (intr_loc >> 1)) == 0)
+ if (!(intr_loc & ~CMD_INTR_PENDING))
goto out;
for (hp_slot = 0; hp_slot < ctrl->num_slots; hp_slot++) {
- /* To find out which slot has interrupt pending */
- if ((intr_loc >> hp_slot) & 0x01) {
- temp_dword = shpc_readl(ctrl, SLOT_REG(hp_slot));
- dbg("%s: Slot %x with intr, slot register = %x\n",
- __FUNCTION__, hp_slot, temp_dword);
- if ((php_ctlr->switch_change_callback) &&
- (temp_dword & MRL_CHANGE_DETECTED))
- schedule_flag += php_ctlr->switch_change_callback(
- hp_slot, php_ctlr->callback_instance_id);
- if ((php_ctlr->attention_button_callback) &&
- (temp_dword & BUTTON_PRESS_DETECTED))
- schedule_flag += php_ctlr->attention_button_callback(
- hp_slot, php_ctlr->callback_instance_id);
- if ((php_ctlr->presence_change_callback) &&
- (temp_dword & PRSNT_CHANGE_DETECTED))
- schedule_flag += php_ctlr->presence_change_callback(
- hp_slot , php_ctlr->callback_instance_id);
- if ((php_ctlr->power_fault_callback) &&
- (temp_dword & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED)))
- schedule_flag += php_ctlr->power_fault_callback(
- hp_slot, php_ctlr->callback_instance_id);
-
- /* Clear all slot events */
- temp_dword &= ~SLOT_REG_RSVDZ_MASK;
- shpc_writel(ctrl, SLOT_REG(hp_slot), temp_dword);
-
- intr_loc2 = shpc_readl(ctrl, INTR_LOC);
- dbg("%s: intr_loc2 = %x\n",__FUNCTION__, intr_loc2);
- }
+ /* To find out which slot has interrupt pending */
+ if (!(intr_loc & SLOT_INTR_PENDING(hp_slot)))
+ continue;
+
+ slot_reg = shpc_readl(ctrl, SLOT_REG(hp_slot));
+ dbg("%s: Slot %x with intr, slot register = %x\n",
+ __FUNCTION__, hp_slot, slot_reg);
+
+ if (slot_reg & MRL_CHANGE_DETECTED)
+ php_ctlr->switch_change_callback(
+ hp_slot, php_ctlr->callback_instance_id);
+
+ if (slot_reg & BUTTON_PRESS_DETECTED)
+ php_ctlr->attention_button_callback(
+ hp_slot, php_ctlr->callback_instance_id);
+
+ if (slot_reg & PRSNT_CHANGE_DETECTED)
+ php_ctlr->presence_change_callback(
+ hp_slot , php_ctlr->callback_instance_id);
+
+ if (slot_reg & (ISO_PFAULT_DETECTED | CON_PFAULT_DETECTED))
+ php_ctlr->power_fault_callback(
+ hp_slot, php_ctlr->callback_instance_id);
+
+ /* Clear all slot events */
+ slot_reg &= ~SLOT_REG_RSVDZ_MASK;
+ shpc_writel(ctrl, SLOT_REG(hp_slot), slot_reg);
}
out:
if (!shpchp_poll_mode) {
/* Unmask Global Interrupt Mask */
- temp_dword = shpc_readl(ctrl, SERR_INTR_ENABLE);
- temp_dword &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
- shpc_writel(ctrl, SERR_INTR_ENABLE, temp_dword);
+ serr_int = shpc_readl(ctrl, SERR_INTR_ENABLE);
+ serr_int &= ~(GLOBAL_INTR_MASK | SERR_INTR_RSVDZ_MASK);
+ shpc_writel(ctrl, SERR_INTR_ENABLE, serr_int);
}
return IRQ_HANDLED;
void *instance_id = ctrl;
int rc, num_slots = 0;
u8 hp_slot;
- static int first = 1;
u32 shpc_base_offset;
u32 tempdword, slot_reg, slot_config;
u8 i;
ctrl->mmio_size = 0x24 + 0x4 * num_slots;
}
- if (first) {
- spin_lock_init(&hpc_event_lock);
- first = 0;
- }
-
info("HPC vendor_id %x device_id %x ss_vid %x ss_did %x\n", pdev->vendor, pdev->device, pdev->subsystem_vendor,
pdev->subsystem_device);
} else
php_ctlr->irq = pdev->irq;
- rc = request_irq(php_ctlr->irq, shpc_isr, SA_SHIRQ, MY_NAME, (void *) ctrl);
+ rc = request_irq(php_ctlr->irq, shpc_isr, IRQF_SHARED, MY_NAME, (void *) ctrl);
dbg("%s: request_irq %d for hpc%d (returns %d)\n", __FUNCTION__, php_ctlr->irq, ctlr_seq_num, rc);
if (rc) {
err("Can't get irq %d for the hotplug controller\n", php_ctlr->irq);
projects / linux-2.6 / blobdiff