#endif /* CONFIG_RT61PCI_RFKILL */
#ifdef CONFIG_RT61PCI_LEDS
-static void rt61pci_led_brightness(struct led_classdev *led_cdev,
+static void rt61pci_brightness_set(struct led_classdev *led_cdev,
enum led_brightness brightness)
{
struct rt2x00_led *led =
brightness / (LED_FULL / 6), 0);
}
}
-#else
-#define rt61pci_led_brightness NULL
+
+static int rt61pci_blink_set(struct led_classdev *led_cdev,
+ unsigned long *delay_on,
+ unsigned long *delay_off)
+{
+ struct rt2x00_led *led =
+ container_of(led_cdev, struct rt2x00_led, led_dev);
+ u32 reg;
+
+ rt2x00pci_register_read(led->rt2x00dev, MAC_CSR14, ®);
+ rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, *delay_on);
+ rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, *delay_off);
+ rt2x00pci_register_write(led->rt2x00dev, MAC_CSR14, reg);
+
+ return 0;
+}
#endif /* CONFIG_RT61PCI_LEDS */
/*
rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
!(filter_flags & FIF_PROMISC_IN_BSS));
rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
- !(filter_flags & FIF_PROMISC_IN_BSS));
+ !(filter_flags & FIF_PROMISC_IN_BSS) &&
+ !rt2x00dev->intf_ap_count);
rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
!(filter_flags & FIF_ALLMULTI));
struct queue_entry_priv_pci_tx *priv_tx = entry->priv_data;
u32 word;
- rt2x00_desc_read(priv_tx->desc, 1, &word);
- rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
- rt2x00_desc_write(priv_tx->desc, 1, word);
-
- rt2x00_desc_read(priv_tx->desc, 5, &word);
- rt2x00_set_field32(&word, TXD_W5_PID_TYPE, entry->queue->qid);
- rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, entry->entry_idx);
- rt2x00_desc_write(priv_tx->desc, 5, word);
-
- rt2x00_desc_read(priv_tx->desc, 6, &word);
- rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
- priv_tx->data_dma);
- rt2x00_desc_write(priv_tx->desc, 6, word);
-
rt2x00_desc_read(priv_tx->desc, 0, &word);
rt2x00_set_field32(&word, TXD_W0_VALID, 0);
rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
- rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
- rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
- rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
- rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
-
/*
* Invalidate all Shared Keys (SEC_CSR0),
* and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
*/
static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
struct sk_buff *skb,
- struct txentry_desc *txdesc,
- struct ieee80211_tx_control *control)
+ struct txentry_desc *txdesc)
{
struct skb_frame_desc *skbdesc = get_skb_frame_desc(skb);
+ struct queue_entry_priv_pci_tx *entry_priv = skbdesc->entry->priv_data;
__le32 *txd = skbdesc->desc;
u32 word;
rt2x00_set_field32(&word, TXD_W1_CWMAX, txdesc->cw_max);
rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
+ rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
rt2x00_desc_write(txd, 1, word);
rt2x00_desc_read(txd, 2, &word);
rt2x00_desc_write(txd, 2, word);
rt2x00_desc_read(txd, 5, &word);
+ rt2x00_set_field32(&word, TXD_W5_PID_TYPE, skbdesc->entry->queue->qid);
+ rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE,
+ skbdesc->entry->entry_idx);
rt2x00_set_field32(&word, TXD_W5_TX_POWER,
TXPOWER_TO_DEV(rt2x00dev->tx_power));
rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
rt2x00_desc_write(txd, 5, word);
+ rt2x00_desc_read(txd, 6, &word);
+ rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
+ entry_priv->data_dma);
+ rt2x00_desc_write(txd, 6, word);
+
if (skbdesc->desc_len > TXINFO_SIZE) {
rt2x00_desc_read(txd, 11, &word);
rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, skbdesc->data_len);
test_bit(ENTRY_TXD_OFDM_RATE, &txdesc->flags));
rt2x00_set_field32(&word, TXD_W0_IFS, txdesc->ifs);
rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
- !!(control->flags &
- IEEE80211_TXCTL_LONG_RETRY_LIMIT));
+ test_bit(ENTRY_TXD_RETRY_MODE, &txdesc->flags));
rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, skbdesc->data_len);
rt2x00_set_field32(&word, TXD_W0_BURST,
* TX data initialization
*/
static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
- const unsigned int queue)
+ const enum data_queue_qid queue)
{
u32 reg;
- if (queue == RT2X00_BCN_QUEUE_BEACON) {
+ if (queue == QID_BEACON) {
/*
* For Wi-Fi faily generated beacons between participating
* stations. Set TBTT phase adaptive adjustment step to 8us.
}
rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0,
- (queue == IEEE80211_TX_QUEUE_DATA0));
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1,
- (queue == IEEE80211_TX_QUEUE_DATA1));
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2,
- (queue == IEEE80211_TX_QUEUE_DATA2));
- rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3,
- (queue == IEEE80211_TX_QUEUE_DATA3));
+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, (queue == QID_AC_BE));
+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, (queue == QID_AC_BK));
+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, (queue == QID_AC_VI));
+ rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, (queue == QID_AC_VO));
rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
}
rt2x00_desc_read(priv_rx->desc, 0, &word0);
rt2x00_desc_read(priv_rx->desc, 1, &word1);
- rxdesc->flags = 0;
if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
rxdesc->rssi = rt61pci_agc_to_rssi(entry->queue->rt2x00dev, word1);
rxdesc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
- rxdesc->dev_flags = 0;
if (rt2x00_get_field32(word0, RXD_W0_OFDM))
rxdesc->dev_flags |= RXDONE_SIGNAL_PLCP;
if (rt2x00_get_field32(word0, RXD_W0_MY_BSS))
"TX status report missed for entry %d\n",
entry_done->entry_idx);
- txdesc.status = TX_FAIL_OTHER;
+ txdesc.flags = 0;
+ __set_bit(TXDONE_UNKNOWN, &txdesc.flags);
txdesc.retry = 0;
rt2x00pci_txdone(rt2x00dev, entry_done, &txdesc);
/*
* Obtain the status about this packet.
*/
- txdesc.status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
+ txdesc.flags = 0;
+ switch (rt2x00_get_field32(reg, STA_CSR4_TX_RESULT)) {
+ case 0: /* Success, maybe with retry */
+ __set_bit(TXDONE_SUCCESS, &txdesc.flags);
+ break;
+ case 6: /* Failure, excessive retries */
+ __set_bit(TXDONE_EXCESSIVE_RETRY, &txdesc.flags);
+ /* Don't break, this is a failed frame! */
+ default: /* Failure */
+ __set_bit(TXDONE_FAILURE, &txdesc.flags);
+ }
txdesc.retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
rt2x00pci_txdone(rt2x00dev, entry, &txdesc);
*/
#ifdef CONFIG_RT61PCI_LEDS
rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
-
value = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
- switch (value) {
- case LED_MODE_TXRX_ACTIVITY:
- case LED_MODE_ASUS:
- case LED_MODE_ALPHA:
- case LED_MODE_DEFAULT:
- rt2x00dev->led_flags =
- LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC;
- break;
- case LED_MODE_SIGNAL_STRENGTH:
- rt2x00dev->led_flags =
- LED_SUPPORT_RADIO | LED_SUPPORT_ASSOC |
- LED_SUPPORT_QUALITY;
- break;
+ rt2x00dev->led_radio.rt2x00dev = rt2x00dev;
+ rt2x00dev->led_radio.type = LED_TYPE_RADIO;
+ rt2x00dev->led_radio.led_dev.brightness_set =
+ rt61pci_brightness_set;
+ rt2x00dev->led_radio.led_dev.blink_set =
+ rt61pci_blink_set;
+ rt2x00dev->led_radio.flags = LED_INITIALIZED;
+
+ rt2x00dev->led_assoc.rt2x00dev = rt2x00dev;
+ rt2x00dev->led_assoc.type = LED_TYPE_ASSOC;
+ rt2x00dev->led_assoc.led_dev.brightness_set =
+ rt61pci_brightness_set;
+ rt2x00dev->led_assoc.led_dev.blink_set =
+ rt61pci_blink_set;
+ rt2x00dev->led_assoc.flags = LED_INITIALIZED;
+
+ if (value == LED_MODE_SIGNAL_STRENGTH) {
+ rt2x00dev->led_qual.rt2x00dev = rt2x00dev;
+ rt2x00dev->led_qual.type = LED_TYPE_QUALITY;
+ rt2x00dev->led_qual.led_dev.brightness_set =
+ rt61pci_brightness_set;
+ rt2x00dev->led_qual.led_dev.blink_set =
+ rt61pci_blink_set;
+ rt2x00dev->led_qual.flags = LED_INITIALIZED;
}
rt2x00_set_field16(&rt2x00dev->led_mcu_reg, MCU_LEDCS_LED_MODE, value);
*/
rt2x00dev->hw->flags =
IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
- IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
+ IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
+ IEEE80211_HW_SIGNAL_DBM;
rt2x00dev->hw->extra_tx_headroom = 0;
- rt2x00dev->hw->max_signal = MAX_SIGNAL;
- rt2x00dev->hw->max_rssi = MAX_RX_SSI;
- rt2x00dev->hw->queues = 4;
SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
}
static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
- struct ieee80211_tx_control *control)
+ struct ieee80211_tx_control *control)
{
struct rt2x00_dev *rt2x00dev = hw->priv;
struct rt2x00_intf *intf = vif_to_intf(control->vif);
+ struct queue_entry_priv_pci_tx *priv_tx;
struct skb_frame_desc *skbdesc;
+ struct txentry_desc txdesc;
unsigned int beacon_base;
u32 reg;
return -ENOBUFS;
/*
- * We need to append the descriptor in front of the
- * beacon frame.
+ * Copy all TX descriptor information into txdesc,
+ * after that we are free to use the skb->cb array
+ * for our information.
*/
- if (skb_headroom(skb) < intf->beacon->queue->desc_size) {
- if (pskb_expand_head(skb, intf->beacon->queue->desc_size,
- 0, GFP_ATOMIC)) {
- dev_kfree_skb(skb);
- return -ENOMEM;
- }
- }
+ intf->beacon->skb = skb;
+ rt2x00queue_create_tx_descriptor(intf->beacon, &txdesc, control);
- /*
- * Add the descriptor in front of the skb.
- */
- skb_push(skb, intf->beacon->queue->desc_size);
- memset(skb->data, 0, intf->beacon->queue->desc_size);
+ priv_tx = intf->beacon->priv_data;
+ memset(priv_tx->desc, 0, intf->beacon->queue->desc_size);
/*
* Fill in skb descriptor
skbdesc = get_skb_frame_desc(skb);
memset(skbdesc, 0, sizeof(*skbdesc));
skbdesc->flags |= FRAME_DESC_DRIVER_GENERATED;
- skbdesc->data = skb->data + intf->beacon->queue->desc_size;
- skbdesc->data_len = skb->len - intf->beacon->queue->desc_size;
- skbdesc->desc = skb->data;
+ skbdesc->data = skb->data;
+ skbdesc->data_len = skb->len;
+ skbdesc->desc = priv_tx->desc;
skbdesc->desc_len = intf->beacon->queue->desc_size;
skbdesc->entry = intf->beacon;
rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
- /*
- * mac80211 doesn't provide the control->queue variable
- * for beacons. Set our own queue identification so
- * it can be used during descriptor initialization.
- */
- control->queue = RT2X00_BCN_QUEUE_BEACON;
- rt2x00lib_write_tx_desc(rt2x00dev, skb, control);
-
/*
* Write entire beacon with descriptor to register,
* and kick the beacon generator.
*/
+ rt2x00queue_write_tx_descriptor(intf->beacon, &txdesc);
beacon_base = HW_BEACON_OFFSET(intf->beacon->entry_idx);
rt2x00pci_register_multiwrite(rt2x00dev, beacon_base,
- skb->data, skb->len);
- rt61pci_kick_tx_queue(rt2x00dev, control->queue);
+ skbdesc->desc, skbdesc->desc_len);
+ rt2x00pci_register_multiwrite(rt2x00dev,
+ beacon_base + skbdesc->desc_len,
+ skbdesc->data, skbdesc->data_len);
+ rt61pci_kick_tx_queue(rt2x00dev, QID_BEACON);
return 0;
}
.link_stats = rt61pci_link_stats,
.reset_tuner = rt61pci_reset_tuner,
.link_tuner = rt61pci_link_tuner,
- .led_brightness = rt61pci_led_brightness,
.write_tx_desc = rt61pci_write_tx_desc,
.write_tx_data = rt2x00pci_write_tx_data,
.kick_tx_queue = rt61pci_kick_tx_queue,
static const struct data_queue_desc rt61pci_queue_bcn = {
.entry_num = 4 * BEACON_ENTRIES,
- .data_size = MGMT_FRAME_SIZE,
+ .data_size = 0, /* No DMA required for beacons */
.desc_size = TXINFO_SIZE,
.priv_size = sizeof(struct queue_entry_priv_pci_tx),
};
.max_ap_intf = 4,
.eeprom_size = EEPROM_SIZE,
.rf_size = RF_SIZE,
+ .tx_queues = NUM_TX_QUEUES,
.rx = &rt61pci_queue_rx,
.tx = &rt61pci_queue_tx,
.bcn = &rt61pci_queue_bcn,
projects / linux-2.6 / blobdiff