Supported chipsets: RT2460.
*/
-/*
- * Set enviroment defines for rt2x00.h
- */
-#define DRV_NAME "rt2400pci"
-
#include <linux/delay.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
* the access attempt is considered to have failed,
* and we will print an error.
*/
-static u32 rt2400pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
+static u32 rt2400pci_bbp_check(struct rt2x00_dev *rt2x00dev)
{
u32 reg;
unsigned int i;
return reg;
}
-static void rt2400pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
+static void rt2400pci_bbp_write(struct rt2x00_dev *rt2x00dev,
const unsigned int word, const u8 value)
{
u32 reg;
rt2x00pci_register_write(rt2x00dev, BBPCSR, reg);
}
-static void rt2400pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
+static void rt2400pci_bbp_read(struct rt2x00_dev *rt2x00dev,
const unsigned int word, u8 *value)
{
u32 reg;
*value = rt2x00_get_field32(reg, BBPCSR_VALUE);
}
-static void rt2400pci_rf_write(const struct rt2x00_dev *rt2x00dev,
+static void rt2400pci_rf_write(struct rt2x00_dev *rt2x00dev,
const unsigned int word, const u32 value)
{
u32 reg;
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
#define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
-static void rt2400pci_read_csr(const struct rt2x00_dev *rt2x00dev,
+static void rt2400pci_read_csr(struct rt2x00_dev *rt2x00dev,
const unsigned int word, u32 *data)
{
rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
}
-static void rt2400pci_write_csr(const struct rt2x00_dev *rt2x00dev,
+static void rt2400pci_write_csr(struct rt2x00_dev *rt2x00dev,
const unsigned int word, u32 data)
{
rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
rt2x00pci_register_read(rt2x00dev, GPIOCSR, ®);
return rt2x00_get_field32(reg, GPIOCSR_BIT0);
}
+#else
+#define rt2400pci_rfkill_poll NULL
#endif /* CONFIG_RT2400PCI_RFKILL */
/*
* Configuration handlers.
*/
-static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
+static void rt2400pci_config_mac_addr(struct rt2x00_dev *rt2x00dev,
+ __le32 *mac)
{
- __le32 reg[2];
-
- memset(®, 0, sizeof(reg));
- memcpy(®, addr, ETH_ALEN);
-
- /*
- * The MAC address is passed to us as an array of bytes,
- * that array is little endian, so no need for byte ordering.
- */
- rt2x00pci_register_multiwrite(rt2x00dev, CSR3, ®, sizeof(reg));
+ rt2x00pci_register_multiwrite(rt2x00dev, CSR3, mac,
+ (2 * sizeof(__le32)));
}
-static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
+static void rt2400pci_config_bssid(struct rt2x00_dev *rt2x00dev,
+ __le32 *bssid)
{
- __le32 reg[2];
-
- memset(®, 0, sizeof(reg));
- memcpy(®, bssid, ETH_ALEN);
-
- /*
- * The BSSID is passed to us as an array of bytes,
- * that array is little endian, so no need for byte ordering.
- */
- rt2x00pci_register_multiwrite(rt2x00dev, CSR5, ®, sizeof(reg));
+ rt2x00pci_register_multiwrite(rt2x00dev, CSR5, bssid,
+ (2 * sizeof(__le32)));
}
-static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, int type)
+static void rt2400pci_config_type(struct rt2x00_dev *rt2x00dev, const int type,
+ const int tsf_sync)
{
- struct interface *intf = &rt2x00dev->interface;
u32 reg;
rt2x00pci_register_write(rt2x00dev, CSR14, 0);
*/
rt2x00pci_register_read(rt2x00dev, BCNCSR1, ®);
rt2x00_set_field32(®, BCNCSR1_PRELOAD,
- PREAMBLE + get_duration(IEEE80211_HEADER, 2));
+ PREAMBLE + get_duration(IEEE80211_HEADER, 20));
rt2x00pci_register_write(rt2x00dev, BCNCSR1, reg);
/*
rt2x00_set_field32(®, CSR14_TSF_COUNT, 1);
rt2x00_set_field32(®, CSR14_TBCN, 1);
rt2x00_set_field32(®, CSR14_BEACON_GEN, 0);
- if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
- is_interface_type(intf, IEEE80211_IF_TYPE_AP))
- rt2x00_set_field32(®, CSR14_TSF_SYNC, 2);
- else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
- rt2x00_set_field32(®, CSR14_TSF_SYNC, 1);
- else
- rt2x00_set_field32(®, CSR14_TSF_SYNC, 0);
+ rt2x00_set_field32(®, CSR14_TSF_SYNC, tsf_sync);
rt2x00pci_register_write(rt2x00dev, CSR14, reg);
}
-static void rt2400pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
+static void rt2400pci_config_preamble(struct rt2x00_dev *rt2x00dev,
+ const int short_preamble,
+ const int ack_timeout,
+ const int ack_consume_time)
{
- struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
+ int preamble_mask;
u32 reg;
- u32 preamble;
- u16 value;
- if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
- preamble = SHORT_PREAMBLE;
- else
- preamble = PREAMBLE;
-
- reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
- rt2x00pci_register_write(rt2x00dev, ARCSR1, reg);
+ /*
+ * When short preamble is enabled, we should set bit 0x08
+ */
+ preamble_mask = short_preamble << 3;
rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
- value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
- SHORT_DIFS : DIFS) +
- PLCP + preamble + get_duration(ACK_SIZE, 10);
- rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, value);
- value = SIFS + PLCP + preamble + get_duration(ACK_SIZE, 10);
- rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, value);
+ rt2x00_set_field32(®, TXCSR1_ACK_TIMEOUT, ack_timeout);
+ rt2x00_set_field32(®, TXCSR1_ACK_CONSUME_TIME, ack_consume_time);
rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
- preamble = DEVICE_GET_RATE_FIELD(rate, PREAMBLE) ? 0x08 : 0x00;
-
rt2x00pci_register_read(rt2x00dev, ARCSR2, ®);
- rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble);
+ rt2x00_set_field32(®, ARCSR2_SIGNAL, 0x00 | preamble_mask);
rt2x00_set_field32(®, ARCSR2_SERVICE, 0x04);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 10));
rt2x00pci_register_write(rt2x00dev, ARCSR2, reg);
rt2x00pci_register_read(rt2x00dev, ARCSR3, ®);
- rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble);
+ rt2x00_set_field32(®, ARCSR3_SIGNAL, 0x01 | preamble_mask);
rt2x00_set_field32(®, ARCSR3_SERVICE, 0x04);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 20));
rt2x00pci_register_write(rt2x00dev, ARCSR3, reg);
rt2x00pci_register_read(rt2x00dev, ARCSR4, ®);
- rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble);
+ rt2x00_set_field32(®, ARCSR4_SIGNAL, 0x02 | preamble_mask);
rt2x00_set_field32(®, ARCSR4_SERVICE, 0x04);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 55));
rt2x00pci_register_write(rt2x00dev, ARCSR4, reg);
rt2x00pci_register_read(rt2x00dev, ARCSR5, ®);
- rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble);
+ rt2x00_set_field32(®, ARCSR5_SIGNAL, 0x03 | preamble_mask);
rt2x00_set_field32(®, ARCSR5_SERVICE, 0x84);
rt2x00_set_field32(®, ARCSR2_LENGTH, get_duration(ACK_SIZE, 110));
rt2x00pci_register_write(rt2x00dev, ARCSR5, reg);
}
static void rt2400pci_config_phymode(struct rt2x00_dev *rt2x00dev,
- const int phymode)
+ const int basic_rate_mask)
{
- struct ieee80211_hw_mode *mode;
- struct ieee80211_rate *rate;
-
- rt2x00dev->curr_hwmode = HWMODE_B;
-
- mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
- rate = &mode->rates[mode->num_rates - 1];
-
- rt2400pci_config_rate(rt2x00dev, rate->val2);
+ rt2x00pci_register_write(rt2x00dev, ARCSR1, basic_rate_mask);
}
static void rt2400pci_config_channel(struct rt2x00_dev *rt2x00dev,
- const int index, const int channel)
+ struct rf_channel *rf)
{
- struct rf_channel reg;
-
- /*
- * Fill rf_reg structure.
- */
- memcpy(®, &rt2x00dev->spec.channels[index], sizeof(reg));
-
/*
* Switch on tuning bits.
*/
- rt2x00_set_field32(®.rf1, RF1_TUNER, 1);
- rt2x00_set_field32(®.rf3, RF3_TUNER, 1);
+ rt2x00_set_field32(&rf->rf1, RF1_TUNER, 1);
+ rt2x00_set_field32(&rf->rf3, RF3_TUNER, 1);
- rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
- rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
- rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
+ rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
+ rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
+ rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
/*
* RF2420 chipset don't need any additional actions.
* reference clock rate to activate auto_tune.
* After that we set the value back to the correct channel.
*/
- rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
+ rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
rt2400pci_rf_write(rt2x00dev, 2, 0x000c2a32);
- rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
+ rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
msleep(1);
- rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
- rt2400pci_rf_write(rt2x00dev, 2, reg.rf2);
- rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
+ rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
+ rt2400pci_rf_write(rt2x00dev, 2, rf->rf2);
+ rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
msleep(1);
/*
* Switch off tuning bits.
*/
- rt2x00_set_field32(®.rf1, RF1_TUNER, 0);
- rt2x00_set_field32(®.rf3, RF3_TUNER, 0);
+ rt2x00_set_field32(&rf->rf1, RF1_TUNER, 0);
+ rt2x00_set_field32(&rf->rf3, RF3_TUNER, 0);
- rt2400pci_rf_write(rt2x00dev, 1, reg.rf1);
- rt2400pci_rf_write(rt2x00dev, 3, reg.rf3);
+ rt2400pci_rf_write(rt2x00dev, 1, rf->rf1);
+ rt2400pci_rf_write(rt2x00dev, 3, rf->rf3);
/*
* Clear false CRC during channel switch.
*/
- rt2x00pci_register_read(rt2x00dev, CNT0, ®.rf1);
+ rt2x00pci_register_read(rt2x00dev, CNT0, &rf->rf1);
}
static void rt2400pci_config_txpower(struct rt2x00_dev *rt2x00dev, int txpower)
}
static void rt2400pci_config_antenna(struct rt2x00_dev *rt2x00dev,
- int antenna_tx, int antenna_rx)
+ struct antenna_setup *ant)
{
u8 r1;
u8 r4;
/*
* Configure the TX antenna.
*/
- switch (antenna_tx) {
- case ANTENNA_SW_DIVERSITY:
+ switch (ant->tx) {
case ANTENNA_HW_DIVERSITY:
rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 1);
break;
case ANTENNA_A:
rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 0);
break;
+ case ANTENNA_SW_DIVERSITY:
+ /*
+ * NOTE: We should never come here because rt2x00lib is
+ * supposed to catch this and send us the correct antenna
+ * explicitely. However we are nog going to bug about this.
+ * Instead, just default to antenna B.
+ */
case ANTENNA_B:
rt2x00_set_field8(&r1, BBP_R1_TX_ANTENNA, 2);
break;
/*
* Configure the RX antenna.
*/
- switch (antenna_rx) {
- case ANTENNA_SW_DIVERSITY:
+ switch (ant->rx) {
case ANTENNA_HW_DIVERSITY:
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
break;
case ANTENNA_A:
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 0);
break;
+ case ANTENNA_SW_DIVERSITY:
+ /*
+ * NOTE: We should never come here because rt2x00lib is
+ * supposed to catch this and send us the correct antenna
+ * explicitely. However we are nog going to bug about this.
+ * Instead, just default to antenna B.
+ */
case ANTENNA_B:
rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
break;
}
static void rt2400pci_config_duration(struct rt2x00_dev *rt2x00dev,
- int short_slot_time, int beacon_int)
+ struct rt2x00lib_conf *libconf)
{
u32 reg;
rt2x00pci_register_read(rt2x00dev, CSR11, ®);
- rt2x00_set_field32(®, CSR11_SLOT_TIME,
- short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
+ rt2x00_set_field32(®, CSR11_SLOT_TIME, libconf->slot_time);
rt2x00pci_register_write(rt2x00dev, CSR11, reg);
rt2x00pci_register_read(rt2x00dev, CSR18, ®);
- rt2x00_set_field32(®, CSR18_SIFS, SIFS);
- rt2x00_set_field32(®, CSR18_PIFS,
- short_slot_time ? SHORT_PIFS : PIFS);
+ rt2x00_set_field32(®, CSR18_SIFS, libconf->sifs);
+ rt2x00_set_field32(®, CSR18_PIFS, libconf->pifs);
rt2x00pci_register_write(rt2x00dev, CSR18, reg);
rt2x00pci_register_read(rt2x00dev, CSR19, ®);
- rt2x00_set_field32(®, CSR19_DIFS,
- short_slot_time ? SHORT_DIFS : DIFS);
- rt2x00_set_field32(®, CSR19_EIFS, EIFS);
+ rt2x00_set_field32(®, CSR19_DIFS, libconf->difs);
+ rt2x00_set_field32(®, CSR19_EIFS, libconf->eifs);
rt2x00pci_register_write(rt2x00dev, CSR19, reg);
rt2x00pci_register_read(rt2x00dev, TXCSR1, ®);
rt2x00pci_register_write(rt2x00dev, TXCSR1, reg);
rt2x00pci_register_read(rt2x00dev, CSR12, ®);
- rt2x00_set_field32(®, CSR12_BEACON_INTERVAL, beacon_int * 16);
- rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION, beacon_int * 16);
+ rt2x00_set_field32(®, CSR12_BEACON_INTERVAL,
+ libconf->conf->beacon_int * 16);
+ rt2x00_set_field32(®, CSR12_CFP_MAX_DURATION,
+ libconf->conf->beacon_int * 16);
rt2x00pci_register_write(rt2x00dev, CSR12, reg);
}
static void rt2400pci_config(struct rt2x00_dev *rt2x00dev,
const unsigned int flags,
- struct ieee80211_conf *conf)
+ struct rt2x00lib_conf *libconf)
{
- int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
-
if (flags & CONFIG_UPDATE_PHYMODE)
- rt2400pci_config_phymode(rt2x00dev, conf->phymode);
+ rt2400pci_config_phymode(rt2x00dev, libconf->basic_rates);
if (flags & CONFIG_UPDATE_CHANNEL)
- rt2400pci_config_channel(rt2x00dev, conf->channel_val,
- conf->channel);
+ rt2400pci_config_channel(rt2x00dev, &libconf->rf);
if (flags & CONFIG_UPDATE_TXPOWER)
- rt2400pci_config_txpower(rt2x00dev, conf->power_level);
+ rt2400pci_config_txpower(rt2x00dev,
+ libconf->conf->power_level);
if (flags & CONFIG_UPDATE_ANTENNA)
- rt2400pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
- conf->antenna_sel_rx);
+ rt2400pci_config_antenna(rt2x00dev, &libconf->ant);
if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
- rt2400pci_config_duration(rt2x00dev, short_slot_time,
- conf->beacon_int);
+ rt2400pci_config_duration(rt2x00dev, libconf);
}
static void rt2400pci_config_cw(struct rt2x00_dev *rt2x00dev,
rt2x00_set_field32(®, LEDCSR_ON_PERIOD, 70);
rt2x00_set_field32(®, LEDCSR_OFF_PERIOD, 30);
-
- if (rt2x00dev->led_mode == LED_MODE_TXRX_ACTIVITY) {
- rt2x00_set_field32(®, LEDCSR_LINK, 1);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 0);
- } else if (rt2x00dev->led_mode == LED_MODE_ASUS) {
- rt2x00_set_field32(®, LEDCSR_LINK, 0);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
- } else {
- rt2x00_set_field32(®, LEDCSR_LINK, 1);
- rt2x00_set_field32(®, LEDCSR_ACTIVITY, 1);
- }
-
+ rt2x00_set_field32(®, LEDCSR_LINK,
+ (rt2x00dev->led_mode != LED_MODE_ASUS));
+ rt2x00_set_field32(®, LEDCSR_ACTIVITY,
+ (rt2x00dev->led_mode != LED_MODE_TXRX_ACTIVITY));
rt2x00pci_register_write(rt2x00dev, LEDCSR, reg);
}
/*
* Link tuning
*/
-static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev)
+static void rt2400pci_link_stats(struct rt2x00_dev *rt2x00dev,
+ struct link_qual *qual)
{
u32 reg;
u8 bbp;
* Update FCS error count from register.
*/
rt2x00pci_register_read(rt2x00dev, CNT0, ®);
- rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
+ qual->rx_failed = rt2x00_get_field32(reg, CNT0_FCS_ERROR);
/*
* Update False CCA count from register.
*/
rt2400pci_bbp_read(rt2x00dev, 39, &bbp);
- rt2x00dev->link.false_cca = bbp;
+ qual->false_cca = bbp;
}
static void rt2400pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
*/
rt2400pci_bbp_read(rt2x00dev, 13, ®);
- if (rt2x00dev->link.false_cca > 512 && reg < 0x20) {
+ if (rt2x00dev->link.qual.false_cca > 512 && reg < 0x20) {
rt2400pci_bbp_write(rt2x00dev, 13, ++reg);
rt2x00dev->link.vgc_level = reg;
- } else if (rt2x00dev->link.false_cca < 100 && reg > 0x08) {
+ } else if (rt2x00dev->link.qual.false_cca < 100 && reg > 0x08) {
rt2400pci_bbp_write(rt2x00dev, 13, --reg);
rt2x00dev->link.vgc_level = reg;
}
static void rt2400pci_init_rxring(struct rt2x00_dev *rt2x00dev)
{
struct data_ring *ring = rt2x00dev->rx;
- struct data_desc *rxd;
+ __le32 *rxd;
unsigned int i;
u32 word;
static void rt2400pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
{
struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
- struct data_desc *txd;
+ __le32 *txd;
unsigned int i;
u32 word;
* TX descriptor initialization
*/
static void rt2400pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
- struct data_desc *txd,
+ __le32 *txd,
struct txdata_entry_desc *desc,
struct ieee80211_hdr *ieee80211hdr,
unsigned int length,
rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
rt2x00_set_field32(&word, TXD_W0_ACK,
- !(control->flags & IEEE80211_TXCTL_NO_ACK));
+ test_bit(ENTRY_TXD_ACK, &desc->flags));
rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
rt2x00_set_field32(&word, TXD_W0_RTS,
}
rt2x00pci_register_read(rt2x00dev, TXCSR0, ®);
- if (queue == IEEE80211_TX_QUEUE_DATA0)
- rt2x00_set_field32(®, TXCSR0_KICK_PRIO, 1);
- else if (queue == IEEE80211_TX_QUEUE_DATA1)
- rt2x00_set_field32(®, TXCSR0_KICK_TX, 1);
- else if (queue == IEEE80211_TX_QUEUE_AFTER_BEACON)
- rt2x00_set_field32(®, TXCSR0_KICK_ATIM, 1);
+ rt2x00_set_field32(®, TXCSR0_KICK_PRIO,
+ (queue == IEEE80211_TX_QUEUE_DATA0));
+ rt2x00_set_field32(®, TXCSR0_KICK_TX,
+ (queue == IEEE80211_TX_QUEUE_DATA1));
+ rt2x00_set_field32(®, TXCSR0_KICK_ATIM,
+ (queue == IEEE80211_TX_QUEUE_AFTER_BEACON));
rt2x00pci_register_write(rt2x00dev, TXCSR0, reg);
}
static void rt2400pci_fill_rxdone(struct data_entry *entry,
struct rxdata_entry_desc *desc)
{
- struct data_desc *rxd = entry->priv;
+ __le32 *rxd = entry->priv;
u32 word0;
u32 word2;
{
struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
struct data_entry *entry;
- struct data_desc *txd;
+ __le32 *txd;
u32 word;
int tx_status;
int retry;
tx_status = rt2x00_get_field32(word, TXD_W0_RESULT);
retry = rt2x00_get_field32(word, TXD_W0_RETRY_COUNT);
- rt2x00lib_txdone(entry, tx_status, retry);
-
- /*
- * Make this entry available for reuse.
- */
- entry->flags = 0;
- rt2x00_set_field32(&word, TXD_W0_VALID, 0);
- rt2x00_desc_write(txd, 0, word);
- rt2x00_ring_index_done_inc(ring);
+ rt2x00pci_txdone(rt2x00dev, entry, tx_status, retry);
}
-
- /*
- * If the data ring was full before the txdone handler
- * we must make sure the packet queue in the mac80211 stack
- * is reenabled when the txdone handler has finished.
- */
- entry = ring->entry;
- if (!rt2x00_ring_full(ring))
- ieee80211_wake_queue(rt2x00dev->hw,
- entry->tx_status.control.queue);
}
static irqreturn_t rt2400pci_interrupt(int irq, void *dev_instance)
/*
* Identify default antenna configuration.
*/
- rt2x00dev->hw->conf.antenna_sel_tx =
+ rt2x00dev->default_ant.tx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
- rt2x00dev->hw->conf.antenna_sel_rx =
+ rt2x00dev->default_ant.rx =
rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
+ /*
+ * When the eeprom indicates SW_DIVERSITY use HW_DIVERSITY instead.
+ * I am not 100% sure about this, but the legacy drivers do not
+ * indicate antenna swapping in software is required when
+ * diversity is enabled.
+ */
+ if (rt2x00dev->default_ant.tx == ANTENNA_SW_DIVERSITY)
+ rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY;
+ if (rt2x00dev->default_ant.rx == ANTENNA_SW_DIVERSITY)
+ rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY;
+
/*
* Store led mode, for correct led behaviour.
*/
/*
* Detect if this device has an hardware controlled radio.
*/
+#ifdef CONFIG_RT2400PCI_RFKILL
if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
- __set_bit(DEVICE_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
+ __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
+#endif /* CONFIG_RT2400PCI_RFKILL */
/*
* Check if the BBP tuning should be enabled.
/*
* This device requires the beacon ring
*/
- __set_bit(REQUIRE_BEACON_RING, &rt2x00dev->flags);
+ __set_bit(DRIVER_REQUIRE_BEACON_RING, &rt2x00dev->flags);
/*
* Set the rssi offset.
* - Some filters are set based on interface type.
*/
*total_flags |= FIF_ALLMULTI;
- if (changed_flags & FIF_OTHER_BSS ||
- changed_flags & FIF_PROMISC_IN_BSS)
+ if (*total_flags & FIF_OTHER_BSS ||
+ *total_flags & FIF_PROMISC_IN_BSS)
*total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
*total_flags |= FIF_PROMISC_IN_BSS;
.configure_filter = rt2400pci_configure_filter,
.get_stats = rt2x00mac_get_stats,
.set_retry_limit = rt2400pci_set_retry_limit,
+ .erp_ie_changed = rt2x00mac_erp_ie_changed,
.conf_tx = rt2400pci_conf_tx,
.get_tx_stats = rt2x00mac_get_tx_stats,
.get_tsf = rt2400pci_get_tsf,
.initialize = rt2x00pci_initialize,
.uninitialize = rt2x00pci_uninitialize,
.set_device_state = rt2400pci_set_device_state,
-#ifdef CONFIG_RT2400PCI_RFKILL
.rfkill_poll = rt2400pci_rfkill_poll,
-#endif /* CONFIG_RT2400PCI_RFKILL */
.link_stats = rt2400pci_link_stats,
.reset_tuner = rt2400pci_reset_tuner,
.link_tuner = rt2400pci_link_tuner,
.config_mac_addr = rt2400pci_config_mac_addr,
.config_bssid = rt2400pci_config_bssid,
.config_type = rt2400pci_config_type,
+ .config_preamble = rt2400pci_config_preamble,
.config = rt2400pci_config,
};
static const struct rt2x00_ops rt2400pci_ops = {
- .name = DRV_NAME,
+ .name = KBUILD_MODNAME,
.rxd_size = RXD_DESC_SIZE,
.txd_size = TXD_DESC_SIZE,
.eeprom_size = EEPROM_SIZE,
MODULE_LICENSE("GPL");
static struct pci_driver rt2400pci_driver = {
- .name = DRV_NAME,
+ .name = KBUILD_MODNAME,
.id_table = rt2400pci_device_table,
.probe = rt2x00pci_probe,
.remove = __devexit_p(rt2x00pci_remove),
projects / linux-2.6 / blobdiff