#include <linux/netdevice.h>
#include <linux/wireless.h>
#include <net/mac80211.h>
-#include <linux/netdevice.h>
#include <linux/etherdevice.h>
-#include <linux/delay.h>
#define IWL 4965
#include "iwl-4965.h"
#include "iwl-helpers.h"
+static void iwl_hw_card_show_info(struct iwl_priv *priv);
+
#define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
[IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
IWL_RATE_SISO_##s##M_PLCP, \
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
/* stop HW */
- iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
- rc = iwl_poll_restricted_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
+ iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
+ rc = iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
(1 << 24), 1000);
if (rc < 0)
IWL_ERROR("Can't stop Rx DMA.\n");
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
{
- int rc = 0;
+ int ret;
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
- if (rc) {
+ ret = iwl_grab_nic_access(priv);
+ if (ret) {
spin_unlock_irqrestore(&priv->lock, flags);
- return rc;
+ return ret;
}
if (!pwr_max) {
u32 val;
- rc = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
+ ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
&val);
if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
- iwl_set_bits_mask_restricted_reg(
- priv, APMG_PS_CTRL_REG,
+ iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
~APMG_PS_CTRL_MSK_PWR_SRC);
} else
- iwl_set_bits_mask_restricted_reg(
- priv, APMG_PS_CTRL_REG,
+ iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
~APMG_PS_CTRL_MSK_PWR_SRC);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
- return rc;
+ return ret;
}
static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
unsigned long flags;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
/* stop HW */
- iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
+ iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
- iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
- iwl_write_restricted(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
rxq->dma_addr >> 8);
- iwl_write_restricted(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
+ iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
(priv->hw_setting.shared_phys +
offsetof(struct iwl_shared, val0)) >> 4);
- iwl_write_restricted(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
+ iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
IWL_FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K |
* iwl_write32(priv,CSR_INT_COAL_REG,0);
*/
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
int rc;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc)
goto out;
- iwl_write_restricted(priv, IWL_FH_KW_MEM_ADDR_REG,
+ iwl_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
priv->kw.dma_addr >> 4);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
out:
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (unlikely(rc)) {
IWL_ERROR("TX reset failed");
spin_unlock_irqrestore(&priv->lock, flags);
goto error_reset;
}
- iwl_write_restricted_reg(priv, SCD_TXFACT, 0);
- iwl_release_restricted_access(priv);
+ iwl_write_prph(priv, KDR_SCD_TXFACT, 0);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
rc = iwl4965_kw_init(priv);
return rc;
}
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
- iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG);
+ iwl_read_prph(priv, APMG_CLK_CTRL_REG);
- iwl_write_restricted_reg(priv, APMG_CLK_CTRL_REG,
+ iwl_write_prph(priv, APMG_CLK_CTRL_REG,
APMG_CLK_VAL_DMA_CLK_RQT |
APMG_CLK_VAL_BSM_CLK_RQT);
- iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG);
+ iwl_read_prph(priv, APMG_CLK_CTRL_REG);
udelay(20);
- iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG,
+ iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
iwl_write32(priv, CSR_INT_COALESCING, 512 / 32);
spin_unlock_irqrestore(&priv->lock, flags);
CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc < 0) {
spin_unlock_irqrestore(&priv->lock, flags);
IWL_DEBUG_INFO("Failed to init the card\n");
return rc;
}
- iwl_read_restricted_reg(priv, APMG_PS_CTRL_REG);
- iwl_set_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
+ iwl_read_prph(priv, APMG_PS_CTRL_REG);
+ iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_RESET_REQ);
udelay(5);
- iwl_clear_bits_restricted_reg(priv, APMG_PS_CTRL_REG,
+ iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
APMG_PS_CTRL_VAL_RESET_REQ);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
iwl_hw_card_show_info(priv);
/* reset TFD queues */
for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
spin_lock_irqsave(&priv->lock, flags);
- if (iwl_grab_restricted_access(priv)) {
+ if (iwl_grab_nic_access(priv)) {
spin_unlock_irqrestore(&priv->lock, flags);
continue;
}
- iwl_write_restricted(priv,
+ iwl_write_direct32(priv,
IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
0x0);
- iwl_poll_restricted_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
+ iwl_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
(txq_id), 200);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
}
udelay(10);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (!rc) {
- iwl_write_restricted_reg(priv, APMG_CLK_EN_REG,
+ iwl_write_prph(priv, APMG_CLK_EN_REG,
APMG_CLK_VAL_DMA_CLK_RQT |
APMG_CLK_VAL_BSM_CLK_RQT);
udelay(10);
- iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG,
+ iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
}
clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
*/
static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
{
- iwl_write_restricted(priv, HBUS_TARG_WRPTR,
+ iwl_write_direct32(priv, HBUS_TARG_WRPTR,
(index & 0xff) | (txq_id << 8));
- iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(txq_id), index);
+ iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
}
/*
int txq_id = txq->q.id;
int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
- iwl_write_restricted_reg(priv, SCD_QUEUE_STATUS_BITS(txq_id),
+ iwl_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
(active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
(tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
(scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
priv->chain_noise_data.delta_gain_code[i] =
CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
#endif /* CONFIG_IWLWIFI_SENSITIVITY*/
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
- priv->scd_base_addr = iwl_read_restricted_reg(priv, SCD_SRAM_BASE_ADDR);
+ priv->scd_base_addr = iwl_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
- iwl_write_restricted_mem(priv, a, 0);
+ iwl_write_targ_mem(priv, a, 0);
for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
- iwl_write_restricted_mem(priv, a, 0);
+ iwl_write_targ_mem(priv, a, 0);
for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
- iwl_write_restricted_mem(priv, a, 0);
+ iwl_write_targ_mem(priv, a, 0);
- iwl_write_restricted_reg(priv, SCD_DRAM_BASE_ADDR,
+ iwl_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
(priv->hw_setting.shared_phys +
offsetof(struct iwl_shared, queues_byte_cnt_tbls)) >> 10);
- iwl_write_restricted_reg(priv, SCD_QUEUECHAIN_SEL, 0);
+ iwl_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
/* initiate the queues */
for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
- iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(i), 0);
- iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
- iwl_write_restricted_mem(priv, priv->scd_base_addr +
+ iwl_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
+ iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
+ iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i),
(SCD_WIN_SIZE <<
SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
- iwl_write_restricted_mem(priv, priv->scd_base_addr +
+ iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(i) +
sizeof(u32),
(SCD_FRAME_LIMIT <<
SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
}
- iwl_write_restricted_reg(priv, SCD_INTERRUPT_MASK,
+ iwl_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
(1 << priv->hw_setting.max_txq_num) - 1);
- iwl_write_restricted_reg(priv, SCD_TXFACT,
+ iwl_write_prph(priv, KDR_SCD_TXFACT,
SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
}
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
priv->hw_setting.max_txq_num = iwl_param_queues_num;
priv->hw_setting.ac_queue_count = AC_NUM;
-
- priv->hw_setting.cck_flag = RATE_MCS_CCK_MSK;
priv->hw_setting.tx_cmd_len = sizeof(struct iwl_tx_cmd);
priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
}
/**
- * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.last_used]
+ * iwl_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr]
*
* Does NOT advance any indexes
*/
int iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
{
struct iwl_tfd_frame *bd_tmp = (struct iwl_tfd_frame *)&txq->bd[0];
- struct iwl_tfd_frame *bd = &bd_tmp[txq->q.last_used];
+ struct iwl_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
struct pci_dev *dev = priv->pci_dev;
int i;
int counter = 0;
IWL_GET_BITS(bd->pa[index], tb1_len),
PCI_DMA_TODEVICE);
- if (txq->txb[txq->q.last_used].skb[i]) {
- struct sk_buff *skb = txq->txb[txq->q.last_used].skb[i];
+ if (txq->txb[txq->q.read_ptr].skb[i]) {
+ struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
dev_kfree_skb(skb);
- txq->txb[txq->q.last_used].skb[i] = NULL;
+ txq->txb[txq->q.read_ptr].skb[i] = NULL;
}
}
return 0;
int txq_id = txq->q.id;
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
}
- iwl_write_restricted(priv, FH_MEM_CBBC_QUEUE(txq_id),
+ iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
txq->q.dma_addr >> 8);
- iwl_write_restricted(
+ iwl_write_direct32(
priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
return 0;
}
-void iwl_hw_card_show_info(struct iwl_priv *priv)
+static void iwl_hw_card_show_info(struct iwl_priv *priv)
{
u16 hw_version = priv->eeprom.board_revision_4965;
len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
- tfd_offset[txq->q.first_empty], byte_cnt, len);
+ tfd_offset[txq->q.write_ptr], byte_cnt, len);
- if (txq->q.first_empty < IWL4965_MAX_WIN_SIZE)
+ if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
- tfd_offset[IWL4965_QUEUE_SIZE + txq->q.first_empty],
+ tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
byte_cnt, len);
return 0;
tx->rate_n_flags = iwl_hw_set_rate_n_flags(iwl_rates[rate_index].plcp,
rate_flags);
- if (ieee80211_is_probe_request(fc))
- tx->tx_flags |= TX_CMD_FLG_TSF_MSK;
- else if (ieee80211_is_back_request(fc))
+ if (ieee80211_is_back_request(fc))
tx->tx_flags |= TX_CMD_FLG_ACK_MSK |
TX_CMD_FLG_IMM_BA_RSP_MASK;
#ifdef CONFIG_IWLWIFI_HT
rx_start->byte_count = amsdu->byte_count;
rx_end = (__le32 *) (((u8 *) hdr) + len);
}
- if (len > 2342 || len < 16) {
- IWL_DEBUG_DROP("byte count out of range [16,2342]"
+ if (len > IWL_RX_BUF_SIZE || len < 16) {
+ IWL_WARNING("byte count out of range [16,4K]"
" : %d\n", len);
return;
}
*/
case IEEE80211_STYPE_ASSOC_RESP:
case IEEE80211_STYPE_REASSOC_RESP:
- if (network_packet && iwl_is_associated(priv)) {
+ if (network_packet) {
#ifdef CONFIG_IWLWIFI_HT
u8 *pos = NULL;
struct ieee802_11_elems elems;
agg->wait_for_ba = 0;
IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->ba_seq_ctl);
sh = agg->start_idx - SEQ_TO_INDEX(ba_seq_ctl>>4);
- if (sh < 0) /* tbw something is wrong with indeces */
+ if (sh < 0) /* tbw something is wrong with indices */
sh += 0x100;
/* don't use 64 bits for now */
agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
index = iwl_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
- /* TODO: Need to get this copy more sefely - now good for debug */
+ /* TODO: Need to get this copy more safely - now good for debug */
/*
{
DECLARE_MAC_BUF(mac);
*/
iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
/* releases all the TFDs until the SSN */
- if (txq->q.last_used != (ba_resp_scd_ssn & 0xff))
+ if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff))
iwl_tx_queue_reclaim(priv, ba_resp_scd_flow, index);
}
static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
{
- iwl_write_restricted_reg(priv,
- SCD_QUEUE_STATUS_BITS(txq_id),
+ iwl_write_prph(priv,
+ KDR_SCD_QUEUE_STATUS_BITS(txq_id),
(0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
(1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
}
tbl_dw_addr = priv->scd_base_addr +
SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
- tbl_dw = iwl_read_restricted_mem(priv, tbl_dw_addr);
+ tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
if (txq_id & 0x1)
tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
else
tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
- iwl_write_restricted_mem(priv, tbl_dw_addr, tbl_dw);
+ iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
return 0;
}
iwl_sta_modify_enable_tid_tx(priv, sta_id, tid);
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
- iwl_set_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
+ iwl_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1<<txq_id));
- priv->txq[txq_id].q.last_used = (ssn_idx & 0xff);
- priv->txq[txq_id].q.first_empty = (ssn_idx & 0xff);
+ priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
+ priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
/* supposes that ssn_idx is valid (!= 0xFFF) */
iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
- iwl_write_restricted_mem(priv,
+ iwl_write_targ_mem(priv,
priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
(SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
- iwl_write_restricted_mem(priv, priv->scd_base_addr +
+ iwl_write_targ_mem(priv, priv->scd_base_addr +
SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
(SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
& SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
- iwl_set_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
+ iwl_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
spin_lock_irqsave(&priv->lock, flags);
- rc = iwl_grab_restricted_access(priv);
+ rc = iwl_grab_nic_access(priv);
if (rc) {
spin_unlock_irqrestore(&priv->lock, flags);
return rc;
iwl4965_tx_queue_stop_scheduler(priv, txq_id);
- iwl_clear_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1 << txq_id));
+ iwl_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
- priv->txq[txq_id].q.last_used = (ssn_idx & 0xff);
- priv->txq[txq_id].q.first_empty = (ssn_idx & 0xff);
+ priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
+ priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
/* supposes that ssn_idx is valid (!= 0xFFF) */
iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
- iwl_clear_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
+ iwl_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
iwl4965_txq_ctx_deactivate(priv, txq_id);
iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
- iwl_release_restricted_access(priv);
+ iwl_release_nic_access(priv);
spin_unlock_irqrestore(&priv->lock, flags);
return 0;
}
struct pci_device_id iwl_hw_card_ids[] = {
- {0x8086, 0x4229, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
- {0x8086, 0x4230, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
+ {PCI_DEVICE(0x8086, 0x4229)},
+ {PCI_DEVICE(0x8086, 0x4230)},
{0}
};
-int iwl_eeprom_aqcuire_semaphore(struct iwl_priv *priv)
+int iwl_eeprom_acquire_semaphore(struct iwl_priv *priv)
{
u16 count;
int rc;
CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
EEPROM_SEM_TIMEOUT);
if (rc >= 0) {
- IWL_DEBUG_IO("Aqcuired semaphore after %d tries.\n",
+ IWL_DEBUG_IO("Acquired semaphore after %d tries.\n",
count+1);
return rc;
}
projects / linux-2.6 / blobdiff