#define ATH9K_RXDESC_INTREQ 0x0020
-enum hal_capability_type {
- HAL_CAP_CIPHER = 0,
- HAL_CAP_TKIP_MIC,
- HAL_CAP_TKIP_SPLIT,
- HAL_CAP_PHYCOUNTERS,
- HAL_CAP_DIVERSITY,
- HAL_CAP_PSPOLL,
- HAL_CAP_TXPOW,
- HAL_CAP_PHYDIAG,
- HAL_CAP_MCAST_KEYSRCH,
- HAL_CAP_TSF_ADJUST,
- HAL_CAP_WME_TKIPMIC,
- HAL_CAP_RFSILENT,
- HAL_CAP_ANT_CFG_2GHZ,
- HAL_CAP_ANT_CFG_5GHZ
-};
-
-struct hal_capabilities {
- u32 halChanSpreadSupport:1,
- halChapTuningSupport:1,
- halMicAesCcmSupport:1,
- halMicCkipSupport:1,
- halMicTkipSupport:1,
- halCipherAesCcmSupport:1,
- halCipherCkipSupport:1,
- halCipherTkipSupport:1,
- halVEOLSupport:1,
- halBssIdMaskSupport:1,
- halMcastKeySrchSupport:1,
- halTsfAddSupport:1,
- halChanHalfRate:1,
- halChanQuarterRate:1,
- halHTSupport:1,
- halGTTSupport:1,
- halFastCCSupport:1,
- halRfSilentSupport:1,
- halWowSupport:1,
- halCSTSupport:1,
- halEnhancedPmSupport:1,
- halAutoSleepSupport:1,
- hal4kbSplitTransSupport:1,
- halWowMatchPatternExact:1;
- u32 halWirelessModes;
- u16 halTotalQueues;
- u16 halKeyCacheSize;
- u16 halLow5GhzChan, halHigh5GhzChan;
- u16 halLow2GhzChan, halHigh2GhzChan;
- u16 halNumMRRetries;
- u16 halRtsAggrLimit;
- u8 halTxChainMask;
- u8 halRxChainMask;
- u16 halTxTrigLevelMax;
- u16 halRegCap;
- u8 halNumGpioPins;
- u8 halNumAntCfg2GHz;
- u8 halNumAntCfg5GHz;
-};
-
-struct hal_ops_config {
- int ath_hal_dma_beacon_response_time;
- int ath_hal_sw_beacon_response_time;
- int ath_hal_additional_swba_backoff;
- int ath_hal_6mb_ack;
- int ath_hal_cwmIgnoreExtCCA;
- u8 ath_hal_pciePowerSaveEnable;
- u8 ath_hal_pcieL1SKPEnable;
- u8 ath_hal_pcieClockReq;
- u32 ath_hal_pcieWaen;
- int ath_hal_pciePowerReset;
- u8 ath_hal_pcieRestore;
- u8 ath_hal_analogShiftReg;
- u8 ath_hal_htEnable;
- u32 ath_hal_ofdmTrigLow;
- u32 ath_hal_ofdmTrigHigh;
- u32 ath_hal_cckTrigHigh;
- u32 ath_hal_cckTrigLow;
- u32 ath_hal_enableANI;
- u8 ath_hal_noiseImmunityLvl;
- u32 ath_hal_ofdmWeakSigDet;
- u32 ath_hal_cckWeakSigThr;
- u8 ath_hal_spurImmunityLvl;
- u8 ath_hal_firStepLvl;
- int8_t ath_hal_rssiThrHigh;
- int8_t ath_hal_rssiThrLow;
- u16 ath_hal_diversityControl;
- u16 ath_hal_antennaSwitchSwap;
- int ath_hal_serializeRegMode;
- int ath_hal_intrMitigation;
+enum wireless_mode {
+ ATH9K_MODE_11A = 0,
+ ATH9K_MODE_11B = 2,
+ ATH9K_MODE_11G = 3,
+ ATH9K_MODE_11NA_HT20 = 6,
+ ATH9K_MODE_11NG_HT20 = 7,
+ ATH9K_MODE_11NA_HT40PLUS = 8,
+ ATH9K_MODE_11NA_HT40MINUS = 9,
+ ATH9K_MODE_11NG_HT40PLUS = 10,
+ ATH9K_MODE_11NG_HT40MINUS = 11,
+ ATH9K_MODE_MAX
+};
+
+enum ath9k_hw_caps {
+ ATH9K_HW_CAP_CHAN_SPREAD = BIT(0),
+ ATH9K_HW_CAP_MIC_AESCCM = BIT(1),
+ ATH9K_HW_CAP_MIC_CKIP = BIT(2),
+ ATH9K_HW_CAP_MIC_TKIP = BIT(3),
+ ATH9K_HW_CAP_CIPHER_AESCCM = BIT(4),
+ ATH9K_HW_CAP_CIPHER_CKIP = BIT(5),
+ ATH9K_HW_CAP_CIPHER_TKIP = BIT(6),
+ ATH9K_HW_CAP_VEOL = BIT(7),
+ ATH9K_HW_CAP_BSSIDMASK = BIT(8),
+ ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(9),
+ ATH9K_HW_CAP_CHAN_HALFRATE = BIT(10),
+ ATH9K_HW_CAP_CHAN_QUARTERRATE = BIT(11),
+ ATH9K_HW_CAP_HT = BIT(12),
+ ATH9K_HW_CAP_GTT = BIT(13),
+ ATH9K_HW_CAP_FASTCC = BIT(14),
+ ATH9K_HW_CAP_RFSILENT = BIT(15),
+ ATH9K_HW_CAP_WOW = BIT(16),
+ ATH9K_HW_CAP_CST = BIT(17),
+ ATH9K_HW_CAP_ENHANCEDPM = BIT(18),
+ ATH9K_HW_CAP_AUTOSLEEP = BIT(19),
+ ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(20),
+ ATH9K_HW_CAP_WOW_MATCHPATTERN_EXACT = BIT(21),
+};
+
+enum ath9k_capability_type {
+ ATH9K_CAP_CIPHER = 0,
+ ATH9K_CAP_TKIP_MIC,
+ ATH9K_CAP_TKIP_SPLIT,
+ ATH9K_CAP_PHYCOUNTERS,
+ ATH9K_CAP_DIVERSITY,
+ ATH9K_CAP_TXPOW,
+ ATH9K_CAP_PHYDIAG,
+ ATH9K_CAP_MCAST_KEYSRCH,
+ ATH9K_CAP_TSF_ADJUST,
+ ATH9K_CAP_WME_TKIPMIC,
+ ATH9K_CAP_RFSILENT,
+ ATH9K_CAP_ANT_CFG_2GHZ,
+ ATH9K_CAP_ANT_CFG_5GHZ
+};
+
+struct ath9k_hw_capabilities {
+ u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
+ DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
+ u16 total_queues;
+ u16 keycache_size;
+ u16 low_5ghz_chan, high_5ghz_chan;
+ u16 low_2ghz_chan, high_2ghz_chan;
+ u16 num_mr_retries;
+ u16 rts_aggr_limit;
+ u8 tx_chainmask;
+ u8 rx_chainmask;
+ u16 tx_triglevel_max;
+ u16 reg_cap;
+ u8 num_gpio_pins;
+ u8 num_antcfg_2ghz;
+ u8 num_antcfg_5ghz;
+};
+
+struct ath9k_ops_config {
+ int dma_beacon_response_time;
+ int sw_beacon_response_time;
+ int additional_swba_backoff;
+ int ack_6mb;
+ int cwm_ignore_extcca;
+ u8 pcie_powersave_enable;
+ u8 pcie_l1skp_enable;
+ u8 pcie_clock_req;
+ u32 pcie_waen;
+ int pcie_power_reset;
+ u8 pcie_restore;
+ u8 analog_shiftreg;
+ u8 ht_enable;
+ u32 ofdm_trig_low;
+ u32 ofdm_trig_high;
+ u32 cck_trig_high;
+ u32 cck_trig_low;
+ u32 enable_ani;
+ u8 noise_immunity_level;
+ u32 ofdm_weaksignal_det;
+ u32 cck_weaksignal_thr;
+ u8 spur_immunity_level;
+ u8 firstep_level;
+ int8_t rssi_thr_high;
+ int8_t rssi_thr_low;
+ u16 diversity_control;
+ u16 antenna_switch_swap;
+ int serialize_regmode;
+ int intr_mitigation;
#define SPUR_DISABLE 0
#define SPUR_ENABLE_IOCTL 1
#define SPUR_ENABLE_EEPROM 2
#define AR_BASE_FREQ_5GHZ 4900
#define AR_SPUR_FEEQ_BOUND_HT40 19
#define AR_SPUR_FEEQ_BOUND_HT20 10
- int ath_hal_spurMode;
- u16 ath_hal_spurChans[AR_EEPROM_MODAL_SPURS][2];
+ int spurmode;
+ u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
};
enum ath9k_tx_queue {
TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE = 0x0080,
};
-struct ath9k_txq_info {
- u32 tqi_ver;
- enum ath9k_tx_queue_subtype tqi_subtype;
- enum ath9k_tx_queue_flags tqi_qflags;
- u32 tqi_priority;
- u32 tqi_aifs;
- u32 tqi_cwmin;
- u32 tqi_cwmax;
- u16 tqi_shretry;
- u16 tqi_lgretry;
- u32 tqi_cbrPeriod;
- u32 tqi_cbrOverflowLimit;
- u32 tqi_burstTime;
- u32 tqi_readyTime;
- u32 tqi_compBuf;
-};
-
#define ATH9K_TXQ_USEDEFAULT ((u32) -1)
#define ATH9K_DECOMP_MASK_SIZE 128
ATH9K_PM_UNDEFINED
};
-#define HAL_ANTENNA_MIN_MODE 0
-#define HAL_ANTENNA_FIXED_A 1
-#define HAL_ANTENNA_FIXED_B 2
-#define HAL_ANTENNA_MAX_MODE 3
-
struct ath9k_mib_stats {
u32 ackrcv_bad;
u32 rts_bad;
enum ath9k_ht_extprotspacing ht_extprotspacing;
};
-enum hal_freq_band {
- HAL_FREQ_BAND_5GHZ = 0,
- HAL_FREQ_BAND_2GHZ = 1,
-};
-
enum ath9k_ani_cmd {
ATH9K_ANI_PRESENT = 0x1,
ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2,
PHY_FH,
PHY_OFDM,
PHY_HT,
- PHY_MAX
};
#define PHY_CCK PHY_DS
u8 ah_decompMask[ATH9K_DECOMP_MASK_SIZE];
u32 ah_flags;
enum ath9k_opmode ah_opmode;
- struct hal_ops_config ah_config;
- struct hal_capabilities ah_caps;
+ struct ath9k_ops_config ah_config;
+ struct ath9k_hw_capabilities ah_caps;
int16_t ah_powerLimit;
u16 ah_maxPowerLevel;
u32 ah_tpScale;
#endif
};
-enum wireless_mode {
- WIRELESS_MODE_11a = 0,
- WIRELESS_MODE_11b = 2,
- WIRELESS_MODE_11g = 3,
- WIRELESS_MODE_11NA_HT20 = 6,
- WIRELESS_MODE_11NG_HT20 = 7,
- WIRELESS_MODE_11NA_HT40PLUS = 8,
- WIRELESS_MODE_11NA_HT40MINUS = 9,
- WIRELESS_MODE_11NG_HT40PLUS = 10,
- WIRELESS_MODE_11NG_HT40MINUS = 11,
- WIRELESS_MODE_MAX
-};
-
-enum {
- ATH9K_MODE_SEL_11A = 0x00001,
- ATH9K_MODE_SEL_11B = 0x00002,
- ATH9K_MODE_SEL_11G = 0x00004,
- ATH9K_MODE_SEL_11NG_HT20 = 0x00008,
- ATH9K_MODE_SEL_11NA_HT20 = 0x00010,
- ATH9K_MODE_SEL_11NG_HT40PLUS = 0x00020,
- ATH9K_MODE_SEL_11NG_HT40MINUS = 0x00040,
- ATH9K_MODE_SEL_11NA_HT40PLUS = 0x00080,
- ATH9K_MODE_SEL_11NA_HT40MINUS = 0x00100,
- ATH9K_MODE_SEL_2GHZ = (ATH9K_MODE_SEL_11B |
- ATH9K_MODE_SEL_11G |
- ATH9K_MODE_SEL_11NG_HT20),
- ATH9K_MODE_SEL_5GHZ = (ATH9K_MODE_SEL_11A |
- ATH9K_MODE_SEL_11NA_HT20),
- ATH9K_MODE_SEL_ALL = 0xffffffff
-};
-
struct chan_centers {
u16 synth_center;
u16 ctl_center;
};
int ath_hal_getcapability(struct ath_hal *ah,
- enum hal_capability_type type,
+ enum ath9k_capability_type type,
u32 capability,
u32 *result);
const struct ath9k_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
u32 maxchans, u32 *nchans,
u8 *regclassids,
u32 maxregids, u32 *nregids,
- u16 cc, u32 modeSelect,
+ u16 cc,
bool enableOutdoor,
bool enableExtendedChannels);
u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
bool ath9k_hw_phycounters(struct ath_hal *ah);
bool ath9k_hw_keyreset(struct ath_hal *ah, u16 entry);
bool ath9k_hw_getcapability(struct ath_hal *ah,
- enum hal_capability_type type,
+ enum ath9k_capability_type type,
u32 capability,
u32 *result);
bool ath9k_hw_setcapability(struct ath_hal *ah,
- enum hal_capability_type type,
+ enum ath9k_capability_type type,
u32 capability,
u32 setting,
int *status);
u32 ath9k_regd_get_antenna_allowed(struct ath_hal *ah,
struct ath9k_channel *chan);
u32 ath9k_hw_mhz2ieee(struct ath_hal *ah, u32 freq, u32 flags);
-bool ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
- struct ath9k_txq_info *qInfo);
-bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
- const struct ath9k_txq_info *qInfo);
+bool ath9k_hw_get_txq_props(struct ath_hal *ah, int q,
+ struct ath9k_tx_queue_info *qinfo);
+bool ath9k_hw_set_txq_props(struct ath_hal *ah, int q,
+ const struct ath9k_tx_queue_info *qinfo);
struct ath9k_channel *ath9k_regd_check_channel(struct ath_hal *ah,
const struct ath9k_channel *c);
void ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
bool ath9k_hw_set_txpowerlimit(struct ath_hal *ah, u32 limit);
bool ath9k_regd_is_public_safety_sku(struct ath_hal *ah);
int ath9k_hw_setuptxqueue(struct ath_hal *ah, enum ath9k_tx_queue type,
- const struct ath9k_txq_info *qInfo);
+ const struct ath9k_tx_queue_info *qinfo);
u32 ath9k_hw_numtxpending(struct ath_hal *ah, u32 q);
const char *ath9k_hw_probe(u16 vendorid, u16 devid);
bool ath9k_hw_disable(struct ath_hal *ah);
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