Merge branch 'upstream-linus' of master.kernel.org:/pub/scm/linux/kernel/git/jgarzik...

[linux-2.6] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 46fa105fce837da265f2675c7d490dfa44712156..fb7e2a5f4a088baa0c683f36dfeca1aaf7ff8517 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -137,6 +137,7 @@
 #define   ASIC_REV_5750                         0x04
 #define   ASIC_REV_5752                         0x06
 #define   ASIC_REV_5780                         0x08
+#define   ASIC_REV_5714                         0x09
 #define  GET_CHIP_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 8)
 #define   CHIPREV_5700_AX               0x70
 #define   CHIPREV_5700_BX               0x71
@@ -531,6 +532,8 @@
 #define  MAC_SERDES_CFG_EDGE_SELECT     0x00001000
 #define MAC_SERDES_STAT                        0x00000594
 /* 0x598 --> 0x5b0 unused */
+#define SERDES_RX_CTRL                 0x000005b0      /* 5780/5714 only */
+#define  SERDES_RX_SIG_DETECT           0x00000400
 #define SG_DIG_CTRL                    0x000005b0
 #define  SG_DIG_USING_HW_AUTONEG        0x80000000
 #define  SG_DIG_SOFT_RESET              0x40000000
@@ -985,14 +988,17 @@
 #define  DEFAULT_MB_RDMA_LOW_WATER      0x00000050
 #define  DEFAULT_MB_RDMA_LOW_WATER_5705         0x00000000
 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
+#define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
 #define BUFMGR_MB_MACRX_LOW_WATER      0x00004414
 #define  DEFAULT_MB_MACRX_LOW_WATER      0x00000020
 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
+#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
 #define BUFMGR_MB_HIGH_WATER           0x00004418
 #define  DEFAULT_MB_HIGH_WATER          0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5705     0x00000060
 #define  DEFAULT_MB_HIGH_WATER_JUMBO    0x0000017c
+#define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
 #define BUFMGR_RX_MB_ALLOC_REQ         0x0000441c
 #define  BUFMGR_MB_ALLOC_BIT            0x10000000
 #define BUFMGR_RX_MB_ALLOC_RESP                0x00004420
@@ -1326,6 +1332,8 @@
 #define  GRC_LCLCTRL_CLEARINT          0x00000002
 #define  GRC_LCLCTRL_SETINT            0x00000004
 #define  GRC_LCLCTRL_INT_ON_ATTN       0x00000008
+#define  GRC_LCLCTRL_USE_SIG_DETECT    0x00000010      /* 5714/5780 only */
+#define  GRC_LCLCTRL_USE_EXT_SIG_DETECT        0x00000020      /* 5714/5780 only */
 #define  GRC_LCLCTRL_GPIO_INPUT3       0x00000020
 #define  GRC_LCLCTRL_GPIO_OE3          0x00000040
 #define  GRC_LCLCTRL_GPIO_OUTPUT3      0x00000080
@@ -1504,6 +1512,7 @@
 #define  FWCMD_NICDRV_IPV6ADDR_CHG      0x00000004
 #define  FWCMD_NICDRV_FIX_DMAR          0x00000005
 #define  FWCMD_NICDRV_FIX_DMAW          0x00000006
+#define  FWCMD_NICDRV_ALIVE2            0x0000000d
 #define NIC_SRAM_FW_CMD_LEN_MBOX       0x00000b7c
 #define NIC_SRAM_FW_CMD_DATA_MBOX      0x00000b80
 #define NIC_SRAM_FW_ASF_STATUS_MBOX    0x00000c00
@@ -2046,6 +2055,11 @@ struct tg3 {
        spinlock_t                      lock;
        spinlock_t                      indirect_lock;
 
+       u32                             (*read32) (struct tg3 *, u32);
+       void                            (*write32) (struct tg3 *, u32, u32);
+       u32                             (*read32_mbox) (struct tg3 *, u32);
+       void                            (*write32_mbox) (struct tg3 *, u32,
+                                                        u32);
        void __iomem                    *regs;
        struct net_device               *dev;
        struct pci_dev                  *pdev;
@@ -2057,6 +2071,8 @@ struct tg3 {
        u32                             msg_enable;
 
        /* begin "tx thread" cacheline section */
+       void                            (*write32_tx_mbox) (struct tg3 *, u32,
+                                                           u32);
        u32                             tx_prod;
        u32                             tx_cons;
        u32                             tx_pending;
@@ -2068,6 +2084,8 @@ struct tg3 {
        dma_addr_t                      tx_desc_mapping;
 
        /* begin "rx thread" cacheline section */
+       void                            (*write32_rx_mbox) (struct tg3 *, u32,
+                                                           u32);
        u32                             rx_rcb_ptr;
        u32                             rx_std_ptr;
        u32                             rx_jumbo_ptr;
@@ -2088,6 +2106,8 @@ struct tg3 {
        struct tg3_rx_buffer_desc       *rx_rcb;
        dma_addr_t                      rx_rcb_mapping;
 
+       u32                             rx_pkt_buf_sz;
+
        /* begin "everything else" cacheline(s) section */
        struct net_device_stats         net_stats;
        struct net_device_stats         net_stats_prev;
@@ -2125,7 +2145,7 @@ struct tg3 {
 #define TG3_FLAG_NO_TX_PSEUDO_CSUM     0x00100000
 #define TG3_FLAG_NO_RX_PSEUDO_CSUM     0x00200000
 #define TG3_FLAG_SERDES_WOL_CAP                0x00400000
-#define TG3_FLAG_JUMBO_ENABLE          0x00800000
+#define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
@@ -2155,6 +2175,13 @@ struct tg3 {
 #define TG3_FLG2_5750_PLUS             0x00080000
 #define TG3_FLG2_PROTECTED_NVRAM       0x00100000
 #define TG3_FLG2_USING_MSI             0x00200000
+#define TG3_FLG2_JUMBO_CAPABLE         0x00400000
+#define TG3_FLG2_MII_SERDES            0x00800000
+#define TG3_FLG2_ANY_SERDES            (TG3_FLG2_PHY_SERDES |  \
+                                       TG3_FLG2_MII_SERDES)
+#define TG3_FLG2_PARALLEL_DETECT       0x01000000
+#define TG3_FLG2_ICH_WORKAROUND                0x02000000
+#define TG3_FLG2_5780_CLASS            0x04000000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3
@@ -2202,6 +2229,7 @@ struct tg3 {
 #define PHY_ID_BCM5705                 0x600081a0
 #define PHY_ID_BCM5750                 0x60008180
 #define PHY_ID_BCM5752                 0x60008100
+#define PHY_ID_BCM5714                 0x60008340
 #define PHY_ID_BCM5780                 0x60008350
 #define PHY_ID_BCM8002                 0x60010140
 #define PHY_ID_INVALID                 0xffffffff
@@ -2226,7 +2254,8 @@ struct tg3 {
         (X) == PHY_ID_BCM5411 || (X) == PHY_ID_BCM5701 || \
         (X) == PHY_ID_BCM5703 || (X) == PHY_ID_BCM5704 || \
         (X) == PHY_ID_BCM5705 || (X) == PHY_ID_BCM5750 || \
-        (X) == PHY_ID_BCM8002)
+        (X) == PHY_ID_BCM5752 || (X) == PHY_ID_BCM5714 || \
+        (X) == PHY_ID_BCM5780 || (X) == PHY_ID_BCM8002)
 
        struct tg3_hw_stats             *hw_stats;
        dma_addr_t                      stats_mapping;