Merge branch 'for-linus' of git://one.firstfloor.org/home/andi/git/linux-2.6

[linux-2.6] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 80f59ac7ec58b3fd8ff7c7783bf2ee5e57da3038..dcdfc084966cc5f5756e47ff25b820aa77774b0d 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -131,6 +131,7 @@
 #define  CHIPREV_ID_5752_A0_HW          0x5000
 #define  CHIPREV_ID_5752_A0             0x6000
 #define  CHIPREV_ID_5752_A1             0x6001
+#define  CHIPREV_ID_5714_A2             0x9002
 #define  CHIPREV_ID_5906_A1             0xc001
 #define  GET_ASIC_REV(CHIP_REV_ID)     ((CHIP_REV_ID) >> 12)
 #define   ASIC_REV_5700                         0x07
@@ -1660,6 +1661,7 @@
 
 #define MII_TG3_TEST1                  0x1e
 #define MII_TG3_TEST1_TRIM_EN          0x0010
+#define MII_TG3_TEST1_CRC_EN           0x8000
 
 /* There are two ways to manage the TX descriptors on the tigon3.
  * Either the descriptors are in host DMA'able memory, or they
@@ -2198,7 +2200,6 @@ struct tg3 {
 #define TG3_FLAG_USE_LINKCHG_REG       0x00000008
 #define TG3_FLAG_USE_MI_INTERRUPT      0x00000010
 #define TG3_FLAG_ENABLE_ASF            0x00000020
-#define TG3_FLAG_5701_REG_WRITE_BUG    0x00000040
 #define TG3_FLAG_POLL_SERDES           0x00000080
 #define TG3_FLAG_MBOX_WRITE_REORDER    0x00000100
 #define TG3_FLAG_PCIX_TARGET_HWBUG     0x00000200
@@ -2214,19 +2215,19 @@ struct tg3 {
 #define TG3_FLAG_PCI_32BIT             0x00080000
 #define TG3_FLAG_SRAM_USE_CONFIG       0x00100000
 #define TG3_FLAG_TX_RECOVERY_PENDING   0x00200000
-#define TG3_FLAG_SERDES_WOL_CAP                0x00400000
+#define TG3_FLAG_WOL_CAP               0x00400000
 #define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
 #define TG3_FLAG_IN_RESET_TASK         0x04000000
 #define TG3_FLAG_40BIT_DMA_BUG         0x08000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
-#define TG3_FLAG_GOT_SERDES_FLOWCTL    0x20000000
-#define TG3_FLAG_SPLIT_MODE            0x40000000
+#define TG3_FLAG_SUPPORT_MSI           0x20000000
+#define TG3_FLAG_CHIP_RESETTING                0x40000000
 #define TG3_FLAG_INIT_COMPLETE         0x80000000
        u32                             tg3_flags2;
 #define TG3_FLG2_RESTART_TIMER         0x00000001
-#define TG3_FLG2_HW_TSO_1_BUG          0x00000002
+#define TG3_FLG2_TSO_BUG               0x00000002
 #define TG3_FLG2_NO_ETH_WIRE_SPEED     0x00000004
 #define TG3_FLG2_IS_5788               0x00000008
 #define TG3_FLG2_MAX_RXPEND_64         0x00000010
@@ -2261,9 +2262,6 @@ struct tg3 {
 #define TG3_FLG2_NO_FWARE_REPORTED     0x40000000
 #define TG3_FLG2_PHY_ADJUST_TRIM       0x80000000
 
-       u32                             split_mode_max_reqs;
-#define SPLIT_MODE_5704_MAX_REQ                3
-
        struct timer_list               timer;
        u16                             timer_counter;
        u16                             timer_multiplier;