[TG3]: Walk PCI capability lists.

[linux-2.6] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 5c21f49026c9929507aab64083d6eb233e54d585..c4f845dd1e8b80e4989962b61d517a3235cd917a 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -57,32 +57,7 @@
 #define TG3PCI_IRQ_PIN                 0x0000003d
 #define TG3PCI_MIN_GNT                 0x0000003e
 #define TG3PCI_MAX_LAT                 0x0000003f
-#define TG3PCI_X_CAPS                  0x00000040
-#define  PCIX_CAPS_RELAXED_ORDERING     0x00020000
-#define  PCIX_CAPS_SPLIT_MASK           0x00700000
-#define  PCIX_CAPS_SPLIT_SHIFT          20
-#define  PCIX_CAPS_BURST_MASK           0x000c0000
-#define  PCIX_CAPS_BURST_SHIFT          18
-#define  PCIX_CAPS_MAX_BURST_CPIOB      2
-#define TG3PCI_PM_CAP_PTR              0x00000041
-#define TG3PCI_X_COMMAND               0x00000042
-#define TG3PCI_X_STATUS                        0x00000044
-#define TG3PCI_PM_CAP_ID               0x00000048
-#define TG3PCI_VPD_CAP_PTR             0x00000049
-#define TG3PCI_PM_CAPS                 0x0000004a
-#define TG3PCI_PM_CTRL_STAT            0x0000004c
-#define TG3PCI_BR_SUPP_EXT             0x0000004e
-#define TG3PCI_PM_DATA                 0x0000004f
-#define TG3PCI_VPD_CAP_ID              0x00000050
-#define TG3PCI_MSI_CAP_PTR             0x00000051
-#define TG3PCI_VPD_ADDR_FLAG           0x00000052
-#define  VPD_ADDR_FLAG_WRITE           0x00008000
-#define TG3PCI_VPD_DATA                        0x00000054
-#define TG3PCI_MSI_CAP_ID              0x00000058
-#define TG3PCI_NXT_CAP_PTR             0x00000059
-#define TG3PCI_MSI_CTRL                        0x0000005a
-#define TG3PCI_MSI_ADDR_LOW            0x0000005c
-#define TG3PCI_MSI_ADDR_HIGH           0x00000060
+/* 0x40 --> 0x64 unused */
 #define TG3PCI_MSI_DATA                        0x00000064
 /* 0x66 --> 0x68 unused */
 #define TG3PCI_MISC_HOST_CTRL          0x00000068
@@ -2176,6 +2151,7 @@ struct tg3 {
        dma_addr_t                      tx_desc_mapping;
 
        /* begin "rx thread" cacheline section */
+       struct napi_struct              napi;
        void                            (*write32_rx_mbox) (struct tg3 *, u32,
                                                            u32);
        u32                             rx_rcb_ptr;
@@ -2317,6 +2293,7 @@ struct tg3 {
 
        int                             pm_cap;
        int                             msi_cap;
+       int                             pcix_cap;
 
        /* PHY info */
        u32                             phy_id;