[PATCH] do_notify_parent_cldstop() cleanup

[linux-2.6] / drivers / net / tg3.h

diff --git a/drivers/net/tg3.h b/drivers/net/tg3.h
index 46fa105fce837da265f2675c7d490dfa44712156..c184b773e58543be34027d65810b7fdb2f4f1539 100644 (file)
--- a/drivers/net/tg3.h
+++ b/drivers/net/tg3.h
@@ -985,14 +985,17 @@
 #define  DEFAULT_MB_RDMA_LOW_WATER      0x00000050
 #define  DEFAULT_MB_RDMA_LOW_WATER_5705         0x00000000
 #define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
+#define  DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
 #define BUFMGR_MB_MACRX_LOW_WATER      0x00004414
 #define  DEFAULT_MB_MACRX_LOW_WATER      0x00000020
 #define  DEFAULT_MB_MACRX_LOW_WATER_5705  0x00000010
 #define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
+#define  DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
 #define BUFMGR_MB_HIGH_WATER           0x00004418
 #define  DEFAULT_MB_HIGH_WATER          0x00000060
 #define  DEFAULT_MB_HIGH_WATER_5705     0x00000060
 #define  DEFAULT_MB_HIGH_WATER_JUMBO    0x0000017c
+#define  DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
 #define BUFMGR_RX_MB_ALLOC_REQ         0x0000441c
 #define  BUFMGR_MB_ALLOC_BIT            0x10000000
 #define BUFMGR_RX_MB_ALLOC_RESP                0x00004420
@@ -2046,6 +2049,11 @@ struct tg3 {
        spinlock_t                      lock;
        spinlock_t                      indirect_lock;
 
+       u32                             (*read32) (struct tg3 *, u32);
+       void                            (*write32) (struct tg3 *, u32, u32);
+       u32                             (*read32_mbox) (struct tg3 *, u32);
+       void                            (*write32_mbox) (struct tg3 *, u32,
+                                                        u32);
        void __iomem                    *regs;
        struct net_device               *dev;
        struct pci_dev                  *pdev;
@@ -2057,6 +2065,8 @@ struct tg3 {
        u32                             msg_enable;
 
        /* begin "tx thread" cacheline section */
+       void                            (*write32_tx_mbox) (struct tg3 *, u32,
+                                                           u32);
        u32                             tx_prod;
        u32                             tx_cons;
        u32                             tx_pending;
@@ -2068,6 +2078,8 @@ struct tg3 {
        dma_addr_t                      tx_desc_mapping;
 
        /* begin "rx thread" cacheline section */
+       void                            (*write32_rx_mbox) (struct tg3 *, u32,
+                                                           u32);
        u32                             rx_rcb_ptr;
        u32                             rx_std_ptr;
        u32                             rx_jumbo_ptr;
@@ -2088,6 +2100,8 @@ struct tg3 {
        struct tg3_rx_buffer_desc       *rx_rcb;
        dma_addr_t                      rx_rcb_mapping;
 
+       u32                             rx_pkt_buf_sz;
+
        /* begin "everything else" cacheline(s) section */
        struct net_device_stats         net_stats;
        struct net_device_stats         net_stats_prev;
@@ -2125,7 +2139,7 @@ struct tg3 {
 #define TG3_FLAG_NO_TX_PSEUDO_CSUM     0x00100000
 #define TG3_FLAG_NO_RX_PSEUDO_CSUM     0x00200000
 #define TG3_FLAG_SERDES_WOL_CAP                0x00400000
-#define TG3_FLAG_JUMBO_ENABLE          0x00800000
+#define TG3_FLAG_JUMBO_RING_ENABLE     0x00800000
 #define TG3_FLAG_10_100_ONLY           0x01000000
 #define TG3_FLAG_PAUSE_AUTONEG         0x02000000
 #define TG3_FLAG_BROKEN_CHECKSUMS      0x10000000
@@ -2155,6 +2169,12 @@ struct tg3 {
 #define TG3_FLG2_5750_PLUS             0x00080000
 #define TG3_FLG2_PROTECTED_NVRAM       0x00100000
 #define TG3_FLG2_USING_MSI             0x00200000
+#define TG3_FLG2_JUMBO_CAPABLE         0x00400000
+#define TG3_FLG2_MII_SERDES            0x00800000
+#define TG3_FLG2_ANY_SERDES            (TG3_FLG2_PHY_SERDES |  \
+                                       TG3_FLG2_MII_SERDES)
+#define TG3_FLG2_PARALLEL_DETECT       0x01000000
+#define TG3_FLG2_ICH_WORKAROUND                0x02000000
 
        u32                             split_mode_max_reqs;
 #define SPLIT_MODE_5704_MAX_REQ                3