#define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
#define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
+#define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
#define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
#define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
#define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
+#define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
#define BUFMGR_MB_HIGH_WATER 0x00004418
#define DEFAULT_MB_HIGH_WATER 0x00000060
#define DEFAULT_MB_HIGH_WATER_5705 0x00000060
#define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
+#define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
#define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
#define BUFMGR_MB_ALLOC_BIT 0x10000000
#define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
struct tg3_rx_buffer_desc *rx_rcb;
dma_addr_t rx_rcb_mapping;
+ u32 rx_pkt_buf_sz;
+
/* begin "everything else" cacheline(s) section */
struct net_device_stats net_stats;
struct net_device_stats net_stats_prev;
#define TG3_FLG2_PROTECTED_NVRAM 0x00100000
#define TG3_FLG2_USING_MSI 0x00200000
#define TG3_FLG2_JUMBO_CAPABLE 0x00400000
+#define TG3_FLG2_MII_SERDES 0x00800000
+#define TG3_FLG2_ANY_SERDES (TG3_FLG2_PHY_SERDES | \
+ TG3_FLG2_MII_SERDES)
+#define TG3_FLG2_PARALLEL_DETECT 0x01000000
u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3