#define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
#define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
+#include <asm/mach-types.h>
+#include <asm/arch/cpu.h>
+
+#define SMC_IRQ_TRIGGER_TYPE (( \
+ machine_is_omap_h2() \
+ || machine_is_omap_h3() \
+ || (machine_is_omap_innovator() && !cpu_is_omap1510()) \
+ ) ? IRQT_FALLING : IRQT_RISING)
+
+
#elif defined(CONFIG_SH_SH4202_MICRODEV)
#define SMC_CAN_USE_8BIT 0
#endif
+#ifndef SMC_IRQ_TRIGGER_TYPE
+#define SMC_IRQ_TRIGGER_TYPE IRQT_RISING
+#endif
#ifdef SMC_USE_PXA_DMA
/*
NULL, NULL, NULL};
-/*
- . Transmit status bits
-*/
-#define TS_SUCCESS 0x0001
-#define TS_LOSTCAR 0x0400
-#define TS_LATCOL 0x0200
-#define TS_16COL 0x0010
-
/*
. Receive status bits
*/
#define SMC_GET_FIFO() SMC_inw( ioaddr, FIFO_REG )
#define SMC_GET_PTR() SMC_inw( ioaddr, PTR_REG )
#define SMC_SET_PTR(x) SMC_outw( x, ioaddr, PTR_REG )
+#define SMC_GET_EPH_STATUS() SMC_inw( ioaddr, EPH_STATUS_REG )
#define SMC_GET_RCR() SMC_inw( ioaddr, RCR_REG )
#define SMC_SET_RCR(x) SMC_outw( x, ioaddr, RCR_REG )
#define SMC_GET_REV() SMC_inw( ioaddr, REV_REG )