#include <linux/version.h>
#include <linux/module.h>
#include <linux/netdevice.h>
+#include <linux/dma-mapping.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/pci.h>
#include <linux/in.h>
#include <linux/delay.h>
#include <linux/if_vlan.h>
+#include <linux/mii.h>
#include <asm/irq.h>
* a receive requires one (or two if using 64 bit dma).
*/
-#ifdef CONFIG_SKY2_EC_A1
#define is_ec_a1(hw) \
- ((hw)->chip_id == CHIP_ID_YUKON_EC && \
- (hw)->chip_rev == CHIP_REV_YU_EC_A1)
-#else
-#define is_ec_a1(hw) 0
-#endif
+ unlikely((hw)->chip_id == CHIP_ID_YUKON_EC && \
+ (hw)->chip_rev == CHIP_REV_YU_EC_A1)
-#define RX_LE_SIZE 256
+#define RX_LE_SIZE 512
#define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
#define RX_MAX_PENDING (RX_LE_SIZE/2 - 2)
-#define RX_DEF_PENDING 128
+#define RX_DEF_PENDING RX_MAX_PENDING
#define RX_COPY_THRESHOLD 256
#define TX_RING_SIZE 512
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) },
{ PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) },
+ { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) },
{ 0 }
};
[CHIP_ID_YUKON_LITE - CHIP_ID_YUKON] = "Lite", /* 0xb0 */
[CHIP_ID_YUKON_LP - CHIP_ID_YUKON] = "LP", /* 0xb2 */
[CHIP_ID_YUKON_XL - CHIP_ID_YUKON] = "XL", /* 0xb3 */
+ [CHIP_ID_YUKON_EC_U - CHIP_ID_YUKON] = "EC Ultra", /* 0xb4 */
[CHIP_ID_YUKON_EC - CHIP_ID_YUKON] = "EC", /* 0xb6 */
[CHIP_ID_YUKON_FE - CHIP_ID_YUKON] = "FE", /* 0xb7 */
/* Access to external PHY */
-static void gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
+static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
{
int i;
for (i = 0; i < PHY_RETRIES; i++) {
if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
- return;
+ return 0;
udelay(1);
}
+
printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
+ return -ETIMEDOUT;
}
-static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
+static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
{
int i;
| GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
for (i = 0; i < PHY_RETRIES; i++) {
- if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
- goto ready;
+ if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
+ *val = gma_read16(hw, port, GM_SMI_DATA);
+ return 0;
+ }
+
udelay(1);
}
- printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
-ready:
- return gma_read16(hw, port, GM_SMI_DATA);
+ return -ETIMEDOUT;
+}
+
+static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
+{
+ u16 v;
+
+ if (__gm_phy_read(hw, port, reg, &v) != 0)
+ printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
+ return v;
}
static int sky2_set_power_state(struct sky2_hw *hw, pci_power_t state)
int i;
const u8 *addr = hw->dev[port]->dev_addr;
- sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
- sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
+ sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
+ sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
GMF_RX_CTRL_DEF);
/* Flush Rx MAC FIFO on any flow control or error */
- reg = GMR_FS_ANY_ERR;
- if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev <= 1)
- reg = 0; /* WA dev #4.115 */
+ sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
- sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), reg);
/* Set threshold to 0xa (64 bytes)
* ASF disabled so no need to do WA dev #4.30
*/
/* Configure Tx MAC FIFO */
sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
+
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
+ sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
+ sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
+ if (hw->dev[port]->mtu > ETH_DATA_LEN) {
+ /* set Tx GMAC FIFO Almost Empty Threshold */
+ sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR), 0x180);
+ /* Disable Store & Forward mode for TX */
+ sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
+ }
+ }
+
}
static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, size_t len)
return le;
}
+/* Return high part of DMA address (could be 32 or 64 bit) */
+static inline u32 high32(dma_addr_t a)
+{
+ return (a >> 16) >> 16;
+}
+
/* Build description to hardware about buffer */
static inline void sky2_rx_add(struct sky2_port *sky2, struct ring_info *re)
{
struct sky2_rx_le *le;
- u32 hi = (re->mapaddr >> 16) >> 16;
+ u32 hi = high32(re->mapaddr);
re->idx = sky2->rx_put;
if (sky2->rx_addr64 != hi) {
le->addr = cpu_to_le32(hi);
le->ctrl = 0;
le->opcode = OP_ADDR64 | HW_OWNER;
- sky2->rx_addr64 = hi;
+ sky2->rx_addr64 = high32(re->mapaddr + re->maplen);
}
le = sky2_next_rx(sky2);
}
}
+/* Basic MII support */
+static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+{
+ struct mii_ioctl_data *data = if_mii(ifr);
+ struct sky2_port *sky2 = netdev_priv(dev);
+ struct sky2_hw *hw = sky2->hw;
+ int err = -EOPNOTSUPP;
+
+ if (!netif_running(dev))
+ return -ENODEV; /* Phy still in reset */
+
+ switch(cmd) {
+ case SIOCGMIIPHY:
+ data->phy_id = PHY_ADDR_MARV;
+
+ /* fallthru */
+ case SIOCGMIIREG: {
+ u16 val = 0;
+ spin_lock_bh(&hw->phy_lock);
+ err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
+ spin_unlock_bh(&hw->phy_lock);
+ data->val_out = val;
+ break;
+ }
+
+ case SIOCSMIIREG:
+ if (!capable(CAP_NET_ADMIN))
+ return -EPERM;
+
+ spin_lock_bh(&hw->phy_lock);
+ err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
+ data->val_in);
+ spin_unlock_bh(&hw->phy_lock);
+ break;
+ }
+ return err;
+}
+
#ifdef SKY2_VLAN_TAG_USED
static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
{
RB_RST_SET);
sky2_qset(hw, txqaddr[port], 0x600);
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U)
+ sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), 0x1a0);
+
+
sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
TX_RING_SIZE - 1);
len = skb_headlen(skb);
mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
- addr64 = (mapping >> 16) >> 16;
+ addr64 = high32(mapping);
re = sky2->tx_ring + sky2->tx_prod;
- /* Send high bits if changed */
- if (addr64 != sky2->tx_addr64) {
+ /* Send high bits if changed or crosses boundary */
+ if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
le = get_tx_le(sky2);
le->tx.addr = cpu_to_le32(addr64);
le->ctrl = 0;
le->opcode = OP_ADDR64 | HW_OWNER;
- sky2->tx_addr64 = addr64;
+ sky2->tx_addr64 = high32(mapping + len);
}
/* Check for TCP Segmentation Offload */
struct net_device *dev = sky2->netdev;
unsigned i;
+ if (done == sky2->tx_cons)
+ return;
+
if (unlikely(netif_msg_tx_done(sky2)))
printk(KERN_DEBUG "%s: tx done, up to %u\n",
dev->name, done);
if (netif_msg_ifdown(sky2))
printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
+ /* Stop more packets from being queued */
netif_stop_queue(dev);
+ /* Disable port IRQ */
+ local_irq_disable();
+ hw->intr_mask &= ~((sky2->port == 0) ? Y2_IS_IRQ_PHY1 : Y2_IS_IRQ_PHY2);
+ sky2_write32(hw, B0_IMSK, hw->intr_mask);
+ local_irq_enable();
+
+
sky2_phy_reset(hw, port);
/* Stop transmitter */
/* turn off LED's */
sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
+ synchronize_irq(hw->pdev->irq);
+
sky2_tx_clean(sky2);
sky2_rx_clean(sky2);
unsigned port = sky2->port;
u16 reg;
- /* disable Rx GMAC FIFO flush mode */
- sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RX_F_FL_OFF);
-
/* Enable Transmit FIFO Underrun */
sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
return -EINVAL;
+ if (hw->chip_id == CHIP_ID_YUKON_EC_U && new_mtu > ETH_DATA_LEN)
+ return -EINVAL;
+
if (!netif_running(dev)) {
dev->mtu = new_mtu;
return 0;
}
- local_irq_disable();
sky2_write32(hw, B0_IMSK, 0);
+ dev->trans_start = jiffies; /* prevent tx timeout */
+ netif_stop_queue(dev);
+ netif_poll_disable(hw->dev[0]);
+
ctl = gma_read16(hw, sky2->port, GM_GP_CTRL);
gma_write16(hw, sky2->port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
sky2_rx_stop(sky2);
err = sky2_rx_start(sky2);
gma_write16(hw, sky2->port, GM_GP_CTRL, ctl);
+ netif_poll_disable(hw->dev[0]);
+ netif_wake_queue(dev);
sky2_write32(hw, B0_IMSK, hw->intr_mask);
- sky2_read32(hw, B0_IMSK);
- local_irq_enable();
+
return err;
}
{
struct ring_info *re = sky2->rx_ring + sky2->rx_next;
struct sk_buff *skb = NULL;
- struct net_device *dev;
const unsigned int bufsize = rx_size(sky2);
if (unlikely(netif_msg_rx_status(sky2)))
sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
- if (!(status & GMR_FS_RX_OK) || (status & GMR_FS_ANY_ERR))
+ if (status & GMR_FS_ANY_ERR)
goto error;
+ if (!(status & GMR_FS_RX_OK))
+ goto resubmit;
+
if (length < RX_COPY_THRESHOLD) {
skb = alloc_skb(length + 2, GFP_ATOMIC);
if (!skb)
}
skb_put(skb, length);
- dev = sky2->netdev;
- skb->dev = dev;
- skb->protocol = eth_type_trans(skb, dev);
- dev->last_rx = jiffies;
-
resubmit:
re->skb->ip_summed = CHECKSUM_NONE;
sky2_rx_add(sky2, re);
return skb;
error:
- if (status & GMR_FS_GOOD_FC)
- goto resubmit;
-
if (netif_msg_rx_err(sky2))
printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
sky2->netdev->name, status, length);
goto resubmit;
}
-/* Transmit ring index in reported status block is encoded as:
- *
- * | TXS2 | TXA2 | TXS1 | TXA1
+/*
+ * Check for transmit complete
*/
-static inline u16 tx_index(u8 port, u32 status, u16 len)
+static inline void sky2_tx_check(struct sky2_hw *hw, int port)
{
- if (port == 0)
- return status & 0xfff;
- else
- return ((status >> 24) & 0xff) | (len & 0xf) << 8;
+ struct net_device *dev = hw->dev[port];
+
+ if (dev && netif_running(dev)) {
+ sky2_tx_complete(netdev_priv(dev),
+ sky2_read16(hw, port == 0
+ ? STAT_TXA1_RIDX : STAT_TXA2_RIDX));
+ }
}
/*
BUG_ON(hwidx >= STATUS_RING_SIZE);
rmb();
- do {
- struct sky2_status_le *le = hw->st_le + hw->st_idx;
+ while (hwidx != hw->st_idx) {
+ struct sky2_status_le *le = hw->st_le + hw->st_idx;
+ struct net_device *dev;
struct sky2_port *sky2;
struct sk_buff *skb;
u32 status;
u16 length;
+ u8 op;
- /* Are we done yet? */
- if (hw->st_idx == hwidx) {
- sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
- hwidx = sky2_read16(hw, STAT_PUT_IDX);
- if (hwidx == hw->st_idx)
- break;
- }
-
+ le = hw->st_le + hw->st_idx;
hw->st_idx = (hw->st_idx + 1) % STATUS_RING_SIZE;
- prefetch(&hw->st_le[hw->st_idx]);
+ prefetch(hw->st_le + hw->st_idx);
BUG_ON(le->link >= hw->ports || !hw->dev[le->link]);
- sky2 = netdev_priv(hw->dev[le->link]);
+ BUG_ON(le->link >= 2);
+ dev = hw->dev[le->link];
+ if (dev == NULL || !netif_running(dev))
+ continue;
+
+ sky2 = netdev_priv(dev);
status = le32_to_cpu(le->status);
length = le16_to_cpu(le->length);
+ op = le->opcode & ~HW_OWNER;
+ le->opcode = 0;
- switch (le->opcode & ~HW_OWNER) {
+ switch (op) {
case OP_RXSTAT:
skb = sky2_receive(sky2, length, status);
if (!skb)
break;
+
+ skb->dev = dev;
+ skb->protocol = eth_type_trans(skb, dev);
+ dev->last_rx = jiffies;
+
#ifdef SKY2_VLAN_TAG_USED
if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
vlan_hwaccel_receive_skb(skb,
} else
#endif
netif_receive_skb(skb);
- ++work_done;
+
+ if (++work_done >= to_do)
+ goto exit_loop;
break;
#ifdef SKY2_VLAN_TAG_USED
break;
case OP_TXINDEXLE:
- sky2_tx_complete(sky2,
- tx_index(sky2->port, status, length));
+ /* pick up transmit status later */
break;
default:
if (net_ratelimit())
printk(KERN_WARNING PFX
- "unknown status opcode 0x%x\n",
- le->opcode);
+ "unknown status opcode 0x%x\n", op);
break;
}
+ }
- le->opcode = 0; /* paranoia */
- } while (work_done < to_do);
+exit_loop:
+ sky2_tx_check(hw, 0);
+ sky2_tx_check(hw, 1);
mmiowb();
- *budget -= work_done;
- dev0->quota -= work_done;
if (work_done < to_do) {
/*
* Another chip workaround, need to restart TX timer if status
netif_rx_complete(dev0);
hw->intr_mask |= Y2_IS_STAT_BMU;
sky2_write32(hw, B0_IMSK, hw->intr_mask);
- sky2_read32(hw, B0_IMSK);
+ mmiowb();
+ return 0;
+ } else {
+ *budget -= work_done;
+ dev0->quota -= work_done;
+ return 1;
}
-
- return work_done >= to_do;
-
}
static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
if (status & Y2_IS_STAT_BMU) {
hw->intr_mask &= ~Y2_IS_STAT_BMU;
sky2_write32(hw, B0_IMSK, hw->intr_mask);
- prefetch(&hw->st_le[hw->st_idx]);
- if (netif_rx_schedule_test(dev0))
+ if (likely(__netif_rx_schedule_prep(dev0))) {
+ prefetch(&hw->st_le[hw->st_idx]);
__netif_rx_schedule(dev0);
+ }
}
if (status & Y2_IS_IRQ_PHY1)
{
switch (hw->chip_id) {
case CHIP_ID_YUKON_EC:
+ case CHIP_ID_YUKON_EC_U:
return 125000; /* 125 Mhz */
case CHIP_ID_YUKON_FE:
return 100000; /* 100 Mhz */
SET_MODULE_OWNER(dev);
SET_NETDEV_DEV(dev, &hw->pdev->dev);
+ dev->irq = hw->pdev->irq;
dev->open = sky2_up;
dev->stop = sky2_down;
+ dev->do_ioctl = sky2_ioctl;
dev->hard_start_xmit = sky2_xmit_frame;
dev->get_stats = sky2_get_stats;
dev->set_multicast_list = sky2_set_multicast;
sky2->port = port;
- dev->features |= NETIF_F_LLTX | NETIF_F_TSO;
+ dev->features |= NETIF_F_LLTX;
+ if (hw->chip_id != CHIP_ID_YUKON_EC_U)
+ dev->features |= NETIF_F_TSO;
if (highmem)
dev->features |= NETIF_F_HIGHDMA;
dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
projects / linux-2.6 / blobdiff