Merge upstream kernel into libata 'passthru' branch

[linux-2.6] / drivers / net / skge.h

diff --git a/drivers/net/skge.h b/drivers/net/skge.h
index fced3d2bc07276fc7b7aecc749630095b26e0c53..f1680beb8e68a903d22228755bc84526656d4b1e 100644 (file)
--- a/drivers/net/skge.h
+++ b/drivers/net/skge.h
@@ -214,8 +214,6 @@ enum {
 
 /*     B2_IRQM_HWE_MSK 32 bit  IRQ Moderation HW Error Mask */
 enum {
-       IS_ERR_MSK      = 0x00003fff,/*                 All Error bits */
-
        IS_IRQ_TIST_OV  = 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
        IS_IRQ_SENSOR   = 1<<12, /* IRQ from Sensor (YUKON only) */
        IS_IRQ_MST_ERR  = 1<<11, /* IRQ master error detected */
@@ -230,6 +228,12 @@ enum {
        IS_M2_PAR_ERR   = 1<<2, /* MAC 2 Parity Error */
        IS_R1_PAR_ERR   = 1<<1, /* Queue R1 Parity Error */
        IS_R2_PAR_ERR   = 1<<0, /* Queue R2 Parity Error */
+
+       IS_ERR_MSK      = IS_IRQ_MST_ERR | IS_IRQ_STAT
+                       | IS_NO_STAT_M1 | IS_NO_STAT_M2
+                       | IS_RAM_RD_PAR | IS_RAM_WR_PAR
+                       | IS_M1_PAR_ERR | IS_M2_PAR_ERR
+                       | IS_R1_PAR_ERR | IS_R2_PAR_ERR,
 };
 
 /*     B2_TST_CTRL1     8 bit  Test Control Register 1 */
@@ -1449,10 +1453,12 @@ enum {
        PHY_M_IS_DTE_CHANGE     = 1<<2, /* DTE Power Det. Status Changed */
        PHY_M_IS_POL_CHANGE     = 1<<1, /* Polarity Changed */
        PHY_M_IS_JABBER         = 1<<0, /* Jabber */
-};
 
-#define PHY_M_DEF_MSK  ( PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE | \
-                         PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR)
+       PHY_M_IS_DEF_MSK        = PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
+                                 PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
+
+       PHY_M_IS_AN_MSK         = PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
+};
 
 /*****  PHY_MARV_EXT_CTRL      16 bit r/w      Ext. PHY Specific Ctrl *****/
 enum {
@@ -1509,7 +1515,7 @@ enum {
        PHY_M_LEDC_TX_C_MSB     = 1<<0, /* Tx Control (MSB, 88E1111 only) */
 };
 
-#define PHY_M_LED_PULS_DUR(x)  (       ((x)<<12) & PHY_M_LEDC_PULS_MSK)
+#define PHY_M_LED_PULS_DUR(x)  (((x)<<12) & PHY_M_LEDC_PULS_MSK)
 
 enum {
        PULS_NO_STR     = 0,/* no pulse stretching */
@@ -1522,7 +1528,7 @@ enum {
        PULS_1300MS     = 7,/* 1.3 s to 2.7 s */
 };
 
-#define PHY_M_LED_BLINK_RT(x)  (       ((x)<<8) & PHY_M_LEDC_BL_R_MSK)
+#define PHY_M_LED_BLINK_RT(x)  (((x)<<8) & PHY_M_LEDC_BL_R_MSK)
 
 enum {
        BLINK_42MS      = 0,/* 42 ms */
@@ -1602,9 +1608,9 @@ enum {
        PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
 };
 
-#define PHY_M_FELP_LED2_CTRL(x)        (       ((x)<<8) & PHY_M_FELP_LED2_MSK)
-#define PHY_M_FELP_LED1_CTRL(x)        (       ((x)<<4) & PHY_M_FELP_LED1_MSK)
-#define PHY_M_FELP_LED0_CTRL(x)        (       ((x)<<0) & PHY_M_FELP_LED0_MSK)
+#define PHY_M_FELP_LED2_CTRL(x)        (((x)<<8) & PHY_M_FELP_LED2_MSK)
+#define PHY_M_FELP_LED1_CTRL(x)        (((x)<<4) & PHY_M_FELP_LED1_MSK)
+#define PHY_M_FELP_LED0_CTRL(x)        (((x)<<0) & PHY_M_FELP_LED0_MSK)
 
 enum {
        LED_PAR_CTRL_COLX       = 0x00,
@@ -1640,7 +1646,7 @@ enum {
        PHY_M_MAC_MD_COPPER     = 5,/* Copper only */
        PHY_M_MAC_MD_1000BX     = 7,/* 1000Base-X only */
 };
-#define PHY_M_MAC_MODE_SEL(x)  (       ((x)<<7) & PHY_M_MAC_MD_MSK)
+#define PHY_M_MAC_MODE_SEL(x)  (((x)<<7) & PHY_M_MAC_MD_MSK)
 
 /*****  PHY_MARV_PHY_CTRL (page 3)             16 bit r/w      LED Control Reg. *****/
 enum {
@@ -1650,10 +1656,10 @@ enum {
        PHY_M_LEDC_STA0_MSK     = 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
 };
 
-#define PHY_M_LEDC_LOS_CTRL(x) (       ((x)<<12) & PHY_M_LEDC_LOS_MSK)
-#define PHY_M_LEDC_INIT_CTRL(x)        (       ((x)<<8) & PHY_M_LEDC_INIT_MSK)
-#define PHY_M_LEDC_STA1_CTRL(x)        (       ((x)<<4) & PHY_M_LEDC_STA1_MSK)
-#define PHY_M_LEDC_STA0_CTRL(x)        (       ((x)<<0) & PHY_M_LEDC_STA0_MSK)
+#define PHY_M_LEDC_LOS_CTRL(x) (((x)<<12) & PHY_M_LEDC_LOS_MSK)
+#define PHY_M_LEDC_INIT_CTRL(x)        (((x)<<8) & PHY_M_LEDC_INIT_MSK)
+#define PHY_M_LEDC_STA1_CTRL(x)        (((x)<<4) & PHY_M_LEDC_STA1_MSK)
+#define PHY_M_LEDC_STA0_CTRL(x)        (((x)<<0) & PHY_M_LEDC_STA0_MSK)
 
 /* GMAC registers  */
 /* Port Registers */
@@ -2454,24 +2460,17 @@ struct skge_hw {
 
        u8                   chip_id;
        u8                   chip_rev;
-       u8                   phy_type;
-       u8                   pmd_type;
-       u16                  phy_addr;
+       u8                   copper;
        u8                   ports;
 
        u32                  ram_size;
        u32                  ram_offset;
+       u16                  phy_addr;
 
        struct tasklet_struct ext_tasklet;
        spinlock_t           phy_lock;
 };
 
-
-static inline int iscopper(const struct skge_hw *hw)
-{
-       return (hw->pmd_type == 'T');
-}
-
 enum {
        FLOW_MODE_NONE          = 0, /* No Flow-Control */
        FLOW_MODE_LOC_SEND      = 1, /* Local station sends PAUSE */
@@ -2505,8 +2504,6 @@ struct skge_port {
        dma_addr_t           dma;
        unsigned long        mem_size;
        unsigned int         rx_buf_size;
-
-       struct timer_list    led_blink;
 };
 
 
@@ -2606,17 +2603,6 @@ static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
        skge_write16(hw, SK_GMAC_REG(port,r), v);
 }
 
-static inline void gma_write32(const struct skge_hw *hw, int port, int r, u32 v)
-{
-       skge_write16(hw, SK_GMAC_REG(port, r), (u16) v);
-       skge_write32(hw, SK_GMAC_REG(port, r+4), (u16)(v >> 16));
-}
-
-static inline void gma_write8(const struct skge_hw *hw, int port, int r, u8 v)
-{
-       skge_write8(hw, SK_GMAC_REG(port,r), v);
-}
-
 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
                                    const u8 *addr)
 {