/* S2io Driver name & version. */
static char s2io_driver_name[] = "Neterion";
-static char s2io_driver_version[] = "Version 2.0.2.0";
+static char s2io_driver_version[] = "Version 2.0.3.1";
static inline int RXD_IS_UP2DT(RxD_t *rxdp)
{
static u64 herc_act_dtx_cfg[] = {
/* Set address */
- 0x80000515BA750000ULL, 0x80000515BA7500E0ULL,
+ 0x8000051536750000ULL, 0x80000515367500E0ULL,
/* Write data */
- 0x80000515BA750004ULL, 0x80000515BA7500E4ULL,
+ 0x8000051536750004ULL, 0x80000515367500E4ULL,
/* Set address */
0x80010515003F0000ULL, 0x80010515003F00E0ULL,
/* Write data */
0x80010515003F0004ULL, 0x80010515003F00E4ULL,
/* Set address */
+ 0x801205150D440000ULL, 0x801205150D4400E0ULL,
+ /* Write data */
+ 0x801205150D440004ULL, 0x801205150D4400E4ULL,
+ /* Set address */
0x80020515F2100000ULL, 0x80020515F21000E0ULL,
/* Write data */
0x80020515F2100004ULL, 0x80020515F21000E4ULL,
#ifndef CONFIG_S2IO_NAPI
static unsigned int indicate_max_pkts;
#endif
+/* Frequency of Rx desc syncs expressed as power of 2 */
+static unsigned int rxsync_frequency = 3;
/*
* S2IO device table.
static int s2io_verify_pci_mode(nic_t *nic)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
register u64 val64 = 0;
int mode;
*/
static int s2io_print_pci_mode(nic_t *nic)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
register u64 val64 = 0;
int mode;
struct config_param *config = &nic->config;
*/
if (nic->device_type & XFRAME_II_DEVICE) {
while (herc_act_dtx_cfg[dtx_cnt] != END_SIGN) {
- SPECIAL_REG_WRITE(xena_dtx_cfg[dtx_cnt],
+ SPECIAL_REG_WRITE(herc_act_dtx_cfg[dtx_cnt],
&bar0->dtx_control, UF);
if (dtx_cnt & 0x1)
msleep(1); /* Necessary!! */
writeq(0xffbbffbbffbbffbbULL, &bar0->mc_pause_thresh_q4q7);
/* Disable RMAC PAD STRIPPING */
- add = (void *) &bar0->mac_cfg;
+ add = &bar0->mac_cfg;
val64 = readq(&bar0->mac_cfg);
val64 &= ~(MAC_CFG_RMAC_STRIP_PAD);
writeq(RMAC_CFG_KEY(0x4C0D), &bar0->rmac_cfg_key);
}
/* Enable select interrupts */
- interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | MC_INTR;
+ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
interruptible |= TX_PIC_INTR | RX_PIC_INTR;
interruptible |= TX_MAC_INTR | RX_MAC_INTR;
val64 |= 0x0000800000000000ULL;
writeq(val64, &bar0->gpio_control);
val64 = 0x0411040400000000ULL;
- writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
+ writeq(val64, (void __iomem *)bar0 + 0x2700);
}
/*
config = &nic->config;
/* Disable all interrupts */
- interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR | MC_INTR;
+ interruptible = TX_TRAFFIC_INTR | RX_TRAFFIC_INTR;
interruptible |= TX_PIC_INTR | RX_PIC_INTR;
interruptible |= TX_MAC_INTR | RX_MAC_INTR;
en_dis_able_nic_intrs(nic, interruptible, DISABLE_INTRS);
#ifndef CONFIG_S2IO_NAPI
unsigned long flags;
#endif
+ RxD_t *first_rxdp = NULL;
mac_control = &nic->mac_control;
config = &nic->config;
if (!skb) {
DBG_PRINT(ERR_DBG, "%s: Out of ", dev->name);
DBG_PRINT(ERR_DBG, "memory to allocate SKBs\n");
+ if (first_rxdp) {
+ wmb();
+ first_rxdp->Control_1 |= RXD_OWN_XENA;
+ }
return -ENOMEM;
}
#ifndef CONFIG_2BUFF_MODE
rxdp->Control_2 &= (~MASK_BUFFER0_SIZE);
rxdp->Control_2 |= SET_BUFFER0_SIZE(size);
rxdp->Host_Control = (unsigned long) (skb);
- rxdp->Control_1 |= RXD_OWN_XENA;
+ if (alloc_tab & ((1 << rxsync_frequency) - 1))
+ rxdp->Control_1 |= RXD_OWN_XENA;
off++;
off %= (MAX_RXDS_PER_BLOCK + 1);
mac_control->rings[ring_no].rx_curr_put_info.offset = off;
rxdp->Control_2 |= SET_BUFFER1_SIZE(1); /* dummy. */
rxdp->Control_2 |= BIT(0); /* Set Buffer_Empty bit. */
rxdp->Host_Control = (u64) ((unsigned long) (skb));
- rxdp->Control_1 |= RXD_OWN_XENA;
+ if (alloc_tab & ((1 << rxsync_frequency) - 1))
+ rxdp->Control_1 |= RXD_OWN_XENA;
off++;
mac_control->rings[ring_no].rx_curr_put_info.offset = off;
#endif
rxdp->Control_2 |= SET_RXD_MARKER;
+ if (!(alloc_tab & ((1 << rxsync_frequency) - 1))) {
+ if (first_rxdp) {
+ wmb();
+ first_rxdp->Control_1 |= RXD_OWN_XENA;
+ }
+ first_rxdp = rxdp;
+ }
atomic_inc(&nic->rx_bufs_left[ring_no]);
alloc_tab++;
}
end:
+ /* Transfer ownership of first descriptor to adapter just before
+ * exiting. Before that, use memory barrier so that ownership
+ * and other fields are seen by adapter correctly.
+ */
+ if (first_rxdp) {
+ wmb();
+ first_rxdp->Control_1 |= RXD_OWN_XENA;
+ }
+
return SUCCESS;
}
int pkt_cnt = 0, org_pkts_to_process;
mac_info_t *mac_control;
struct config_param *config;
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) nic->bar0;
+ XENA_dev_config_t __iomem *bar0 = nic->bar0;
u64 val64;
int i;
DBG_PRINT(ERR_DBG, "%s: Device indicates ",
dev->name);
DBG_PRINT(ERR_DBG, "double ECC error!!\n");
- netif_stop_queue(dev);
- schedule_work(&nic->rst_timer_task);
+ if (nic->device_type != XFRAME_II_DEVICE) {
+ netif_stop_queue(dev);
+ schedule_work(&nic->rst_timer_task);
+ }
} else {
nic->mac_control.stats_info->sw_stat.
single_ecc_errs++;
u16 subid, pci_cmd;
/* Back up the PCI-X CMD reg, dont want to lose MMRBC, OST settings */
- if (sp->device_type == XFRAME_I_DEVICE)
- pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
+ pci_read_config_word(sp->pdev, PCIX_COMMAND_REGISTER, &(pci_cmd));
val64 = SW_RESET_ALL;
writeq(val64, &bar0->sw_reset);
*/
msleep(250);
- if (!(sp->device_type & XFRAME_II_DEVICE)) {
- /* Restore the PCI state saved during initializarion. */
- pci_restore_state(sp->pdev);
- pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
+ /* Restore the PCI state saved during initialization. */
+ pci_restore_state(sp->pdev);
+ pci_write_config_word(sp->pdev, PCIX_COMMAND_REGISTER,
pci_cmd);
- } else {
- pci_set_master(sp->pdev);
- }
s2io_init_pci(sp);
msleep(250);
s2io_set_swapper(sp);
/* Clear certain PCI/PCI-X fields after reset */
- pci_read_config_word(sp->pdev, PCI_COMMAND, &pci_cmd);
- pci_cmd &= 0x7FFF; /* Clear parity err detect bit */
- pci_write_config_word(sp->pdev, PCI_COMMAND, pci_cmd);
+ if (sp->device_type == XFRAME_II_DEVICE) {
+ /* Clear parity err detect bit */
+ pci_write_config_word(sp->pdev, PCI_STATUS, 0x8000);
- val64 = readq(&bar0->txpic_int_reg);
- val64 &= ~BIT(62); /* Clearing PCI_STATUS error reflected here */
- writeq(val64, &bar0->txpic_int_reg);
+ /* Clearing PCIX Ecc status register */
+ pci_write_config_dword(sp->pdev, 0x68, 0x7C);
- /* Clearing PCIX Ecc status register */
- pci_write_config_dword(sp->pdev, 0x68, 0);
+ /* Clearing PCI_STATUS error reflected here */
+ writeq(BIT(62), &bar0->txpic_int_reg);
+ }
/* Reset device statistics maintained by OS */
memset(&sp->stats, 0, sizeof (struct net_device_stats));
val64 |= 0x0000800000000000ULL;
writeq(val64, &bar0->gpio_control);
val64 = 0x0411040400000000ULL;
- writeq(val64, (void __iomem *) ((u8 *) bar0 + 0x2700));
+ writeq(val64, (void __iomem *)bar0 + 0x2700);
}
/*
val64 = mac_control->fifos[queue].list_info[put_off].list_phy_addr;
writeq(val64, &tx_fifo->TxDL_Pointer);
- wmb();
-
val64 = (TX_FIFO_LAST_TXD_NUM(frg_cnt) | TX_FIFO_FIRST_LIST |
TX_FIFO_LAST_LIST);
#endif
writeq(val64, &tx_fifo->List_Control);
+ mmiowb();
+
put_off++;
put_off %= mac_control->fifos[queue].tx_curr_put_info.fifo_len + 1;
mac_control->fifos[queue].tx_curr_put_info.offset = put_off;
static void s2io_txpic_intr_handle(nic_t *sp)
{
- XENA_dev_config_t *bar0 = (XENA_dev_config_t *) sp->bar0;
+ XENA_dev_config_t __iomem *bar0 = sp->bar0;
u64 val64;
val64 = readq(&bar0->pic_int_status);
#ifndef CONFIG_S2IO_NAPI
module_param(indicate_max_pkts, int, 0);
#endif
+module_param(rxsync_frequency, int, 0);
/**
* s2io_init_nic - Initialization of the adapter .
INIT_WORK(&sp->set_link_task,
(void (*)(void *)) s2io_set_link, sp);
- if (!(sp->device_type & XFRAME_II_DEVICE)) {
- pci_save_state(sp->pdev);
- }
+ pci_save_state(sp->pdev);
/* Setting swapper control on the NIC, for proper reset operation */
if (s2io_set_swapper(sp)) {
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