}
static void ql_write_common_reg_l(struct ql3_adapter *qdev,
- u32 * reg, u32 value)
+ u32 __iomem *reg, u32 value)
{
unsigned long hw_flags;
spin_lock_irqsave(&qdev->hw_lock, hw_flags);
- writel(value, (u32 *) reg);
+ writel(value, reg);
readl(reg);
spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
return;
}
static void ql_write_common_reg(struct ql3_adapter *qdev,
- u32 * reg, u32 value)
+ u32 __iomem *reg, u32 value)
{
- writel(value, (u32 *) reg);
+ writel(value, reg);
readl(reg);
return;
}
+static void ql_write_nvram_reg(struct ql3_adapter *qdev,
+ u32 __iomem *reg, u32 value)
+{
+ writel(value, reg);
+ readl(reg);
+ udelay(1);
+ return;
+}
+
static void ql_write_page0_reg(struct ql3_adapter *qdev,
- u32 * reg, u32 value)
+ u32 __iomem *reg, u32 value)
{
if (qdev->current_page != 0)
ql_set_register_page(qdev,0);
- writel(value, (u32 *) reg);
+ writel(value, reg);
readl(reg);
return;
}
* Caller holds hw_lock. Only called during init.
*/
static void ql_write_page1_reg(struct ql3_adapter *qdev,
- u32 * reg, u32 value)
+ u32 __iomem *reg, u32 value)
{
if (qdev->current_page != 1)
ql_set_register_page(qdev,1);
- writel(value, (u32 *) reg);
+ writel(value, reg);
readl(reg);
return;
}
* Caller holds hw_lock. Only called during init.
*/
static void ql_write_page2_reg(struct ql3_adapter *qdev,
- u32 * reg, u32 value)
+ u32 __iomem *reg, u32 value)
{
if (qdev->current_page != 2)
ql_set_register_page(qdev,2);
- writel(value, (u32 *) reg);
+ writel(value, reg);
readl(reg);
return;
}
qdev->mem_map_registers;
qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_1;
- ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
+ ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
- ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
+ ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
((ISP_NVRAM_MASK << 16) | qdev->eeprom_cmd_data));
}
qdev->mem_map_registers;
/* Clock in a zero, then do the start bit */
- ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
+ ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
AUBURN_EEPROM_DO_1);
- ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
+ ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
AUBURN_EEPROM_CLK_RISE);
- ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
+ ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
eeprom_cmd_data | AUBURN_EEPROM_DO_1 |
AUBURN_EEPROM_CLK_FALL);
* If the bit changed, then change the DO state to
* match
*/
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
eeprom_cmd_data | dataBit);
previousBit = dataBit;
}
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
eeprom_cmd_data | dataBit |
AUBURN_EEPROM_CLK_RISE);
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
* If the bit changed, then change the DO state to
* match
*/
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
eeprom_cmd_data | dataBit);
previousBit = dataBit;
}
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
eeprom_cmd_data | dataBit |
AUBURN_EEPROM_CLK_RISE);
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->
struct ql3xxx_port_registers __iomem *port_regs =
qdev->mem_map_registers;
qdev->eeprom_cmd_data = AUBURN_EEPROM_CS_0;
- ql_write_common_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
+ ql_write_nvram_reg(qdev, &port_regs->CommonRegs.serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->eeprom_cmd_data);
}
/* Read the data bits */
/* The first bit is a dummy. Clock right over it. */
for (i = 0; i < dataBits; i++) {
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
AUBURN_EEPROM_CLK_RISE);
- ql_write_common_reg(qdev,
+ ql_write_nvram_reg(qdev,
&port_regs->CommonRegs.
serialPortInterfaceReg,
ISP_NVRAM_MASK | qdev->eeprom_cmd_data |
qdev->lrg_buf_next_free = lrg_buf_q_ele;
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.
+ &port_regs->CommonRegs.
rxLargeQProducerIndex,
qdev->lrg_buf_q_producer_index);
}
}
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.
+ &port_regs->CommonRegs.
rxSmallQProducerIndex,
qdev->small_buf_q_producer_index);
}
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.rspQConsumerIndex,
+ &port_regs->CommonRegs.rspQConsumerIndex,
qdev->rsp_consumer_index);
spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
return 1;
}
-static irqreturn_t ql3xxx_isr(int irq, void *dev_id, struct pt_regs *regs)
+static irqreturn_t ql3xxx_isr(int irq, void *dev_id)
{
struct net_device *ndev = dev_id;
"%s: Another function issued a reset to the "
"chip. ISR value = %x.\n", ndev->name, value);
}
- queue_work(qdev->workqueue, &qdev->reset_work);
+ queue_delayed_work(qdev->workqueue, &qdev->reset_work, 0);
spin_unlock(&qdev->adapter_lock);
} else if (value & ISP_IMR_DISABLE_CMPL_INT) {
ql_disable_interrupts(qdev);
qdev->req_producer_index = 0;
wmb();
ql_write_common_reg_l(qdev,
- (u32 *) & port_regs->CommonRegs.reqQProducerIndex,
+ &port_regs->CommonRegs.reqQProducerIndex,
qdev->req_producer_index);
ndev->trans_start = jiffies;
static int ql_init_misc_registers(struct ql3_adapter *qdev)
{
- struct ql3xxx_local_ram_registers *local_ram =
- (struct ql3xxx_local_ram_registers *)qdev->mem_map_registers;
+ struct ql3xxx_local_ram_registers __iomem *local_ram =
+ (void __iomem *)qdev->mem_map_registers;
if(ql_sem_spinlock(qdev, QL_DDR_RAM_SEM_MASK,
(QL_RESOURCE_BITS_BASE_CODE | (qdev->mac_index) *
u32 value;
struct ql3xxx_port_registers __iomem *port_regs = qdev->mem_map_registers;
struct ql3xxx_host_memory_registers __iomem *hmem_regs =
- (struct ql3xxx_host_memory_registers *)port_regs;
+ (void __iomem *)port_regs;
u32 delay = 10;
int status = 0;
qdev->lrg_buf_free_tail = NULL;
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.
+ &port_regs->CommonRegs.
rxSmallQProducerIndex,
qdev->small_buf_q_producer_index);
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.
+ &port_regs->CommonRegs.
rxLargeQProducerIndex,
qdev->lrg_buf_q_producer_index);
"%s: Issue soft reset to chip.\n",
qdev->ndev->name);
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.ispControlStatus,
+ &port_regs->CommonRegs.ispControlStatus,
((ISP_CONTROL_SR << 16) | ISP_CONTROL_SR));
/* Wait 3 seconds for reset to complete. */
printk(KERN_DEBUG PFX
"ql_adapter_reset: clearing RI after reset.\n");
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.
+ &port_regs->CommonRegs.
ispControlStatus,
((ISP_CONTROL_RI << 16) | ISP_CONTROL_RI));
}
if (max_wait_time == 0) {
/* Issue Force Soft Reset */
ql_write_common_reg(qdev,
- (u32 *) & port_regs->CommonRegs.
+ &port_regs->CommonRegs.
ispControlStatus,
((ISP_CONTROL_FSR << 16) |
ISP_CONTROL_FSR));
/*
* Wake up the worker to process this event.
*/
- queue_work(qdev->workqueue, &qdev->tx_timeout_work);
+ queue_delayed_work(qdev->workqueue, &qdev->tx_timeout_work, 0);
}
-static void ql_reset_work(struct ql3_adapter *qdev)
+static void ql_reset_work(struct work_struct *work)
{
+ struct ql3_adapter *qdev =
+ container_of(work, struct ql3_adapter, reset_work.work);
struct net_device *ndev = qdev->ndev;
u32 value;
struct ql_tx_buf_cb *tx_cb;
"%s: clearing NRI after reset.\n",
qdev->ndev->name);
ql_write_common_reg(qdev,
- (u32 *) &
- port_regs->
+ &port_regs->
CommonRegs.
ispControlStatus,
((ISP_CONTROL_RI <<
}
}
-static void ql_tx_timeout_work(struct ql3_adapter *qdev)
+static void ql_tx_timeout_work(struct work_struct *work)
{
- ql_cycle_adapter(qdev,QL_DO_RESET);
+ struct ql3_adapter *qdev =
+ container_of(work, struct ql3_adapter, tx_timeout_work.work);
+
+ ql_cycle_adapter(qdev, QL_DO_RESET);
}
static void ql_get_board_info(struct ql3_adapter *qdev)
SET_MODULE_OWNER(ndev);
SET_NETDEV_DEV(ndev, &pdev->dev);
- ndev->features = NETIF_F_LLTX;
if (pci_using_dac)
ndev->features |= NETIF_F_HIGHDMA;
netif_stop_queue(ndev);
qdev->workqueue = create_singlethread_workqueue(ndev->name);
- INIT_WORK(&qdev->reset_work, (void (*)(void *))ql_reset_work, qdev);
- INIT_WORK(&qdev->tx_timeout_work,
- (void (*)(void *))ql_tx_timeout_work, qdev);
+ INIT_DELAYED_WORK(&qdev->reset_work, ql_reset_work);
+ INIT_DELAYED_WORK(&qdev->tx_timeout_work, ql_tx_timeout_work);
init_timer(&qdev->adapter_timer);
qdev->adapter_timer.function = ql3xxx_timer;
qdev->workqueue = NULL;
}
- iounmap((void *)qdev->mmap_virt_base);
+ iounmap(qdev->mem_map_registers);
pci_release_regions(pdev);
pci_set_drvdata(pdev, NULL);
free_netdev(ndev);