#include <asm/system.h>
static char mv643xx_eth_driver_name[] = "mv643xx_eth";
-static char mv643xx_eth_driver_version[] = "1.0";
+static char mv643xx_eth_driver_version[] = "1.1";
#define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
#define MV643XX_ETH_NAPI
#define MV643XX_ETH_TX_FAST_REFILL
-#undef MV643XX_ETH_COAL
-
-#define MV643XX_ETH_TX_COAL 100
-#ifdef MV643XX_ETH_COAL
-#define MV643XX_ETH_RX_COAL 100
-#endif
#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
#define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
#define MAX_DESCS_PER_SKB 1
#endif
-#define ETH_HW_IP_ALIGN 2
-
/*
* Registers shared between all ports.
*/
#define PORT_STATUS(p) (0x0444 + ((p) << 10))
#define TX_FIFO_EMPTY 0x00000400
#define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
+#define TXQ_FIX_PRIO_CONF(p) (0x044c + ((p) << 10))
+#define TX_BW_RATE(p) (0x0450 + ((p) << 10))
#define TX_BW_MTU(p) (0x0458 + ((p) << 10))
+#define TX_BW_BURST(p) (0x045c + ((p) << 10))
#define INT_CAUSE(p) (0x0460 + ((p) << 10))
-#define INT_RX 0x00000804
+#define INT_TX_END 0x07f80000
+#define INT_RX 0x0007fbfc
#define INT_EXT 0x00000002
#define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
#define INT_EXT_LINK 0x00100000
#define INT_EXT_PHY 0x00010000
#define INT_EXT_TX_ERROR_0 0x00000100
#define INT_EXT_TX_0 0x00000001
-#define INT_EXT_TX 0x00000101
+#define INT_EXT_TX 0x0000ffff
#define INT_MASK(p) (0x0468 + ((p) << 10))
#define INT_MASK_EXT(p) (0x046c + ((p) << 10))
#define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
-#define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
+#define TXQ_FIX_PRIO_CONF_MOVED(p) (0x04dc + ((p) << 10))
+#define TX_BW_RATE_MOVED(p) (0x04e0 + ((p) << 10))
+#define TX_BW_MTU_MOVED(p) (0x04e8 + ((p) << 10))
+#define TX_BW_BURST_MOVED(p) (0x04ec + ((p) << 10))
+#define RXQ_CURRENT_DESC_PTR(p, q) (0x060c + ((p) << 10) + ((q) << 4))
#define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
-#define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
+#define TXQ_CURRENT_DESC_PTR(p, q) (0x06c0 + ((p) << 10) + ((q) << 2))
+#define TXQ_BW_TOKENS(p, q) (0x0700 + ((p) << 10) + ((q) << 4))
+#define TXQ_BW_CONF(p, q) (0x0704 + ((p) << 10) + ((q) << 4))
+#define TXQ_BW_WRR_CONF(p, q) (0x0708 + ((p) << 10) + ((q) << 4))
#define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
#define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
#define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
#define DEFAULT_RX_QUEUE_SIZE 400
#define DEFAULT_TX_QUEUE_SIZE 800
-/* SMI reg */
-#define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
-#define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
-#define SMI_OPCODE_WRITE 0 /* Completion of Read */
-#define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
-
/*
* RX/TX descriptors.
/* global *******************************************************************/
struct mv643xx_eth_shared_private {
+ /*
+ * Ethernet controller base address.
+ */
void __iomem *base;
- /* used to protect SMI_REG, which is shared across ports */
+ /*
+ * Protects access to SMI_REG, which is shared between ports.
+ */
spinlock_t phy_lock;
+ /*
+ * Per-port MBUS window access register value.
+ */
u32 win_protect;
+ /*
+ * Hardware-specific parameters.
+ */
unsigned int t_clk;
+ int extended_rx_coal_limit;
+ int tx_bw_control_moved;
};
};
struct rx_queue {
+ int index;
+
int rx_ring_size;
int rx_desc_count;
struct timer_list rx_oom;
};
-struct mv643xx_eth_private {
- struct mv643xx_eth_shared_private *shared;
- int port_num; /* User Ethernet port number */
-
- struct mv643xx_eth_shared_private *shared_smi;
-
- u32 tx_sram_addr; /* Base address of tx sram area */
- u32 tx_sram_size; /* Size of tx sram area */
+struct tx_queue {
+ int index;
- /* Tx/Rx rings managment indexes fields. For driver use */
-
- /* Next available and first returning Tx resource */
- int tx_curr_desc, tx_used_desc;
+ int tx_ring_size;
-#ifdef MV643XX_ETH_TX_FAST_REFILL
- u32 tx_clean_threshold;
-#endif
+ int tx_desc_count;
+ int tx_curr_desc;
+ int tx_used_desc;
struct tx_desc *tx_desc_area;
dma_addr_t tx_desc_dma;
int tx_desc_area_size;
struct sk_buff **tx_skb;
+};
- struct work_struct tx_timeout_task;
+struct mv643xx_eth_private {
+ struct mv643xx_eth_shared_private *shared;
+ int port_num;
struct net_device *dev;
- struct mib_counters mib_counters;
+
+ struct mv643xx_eth_shared_private *shared_smi;
+ int phy_addr;
+
spinlock_t lock;
- /* Size of Tx Ring per queue */
- int tx_ring_size;
- /* Number of tx descriptors in use */
- int tx_desc_count;
- u32 rx_int_coal;
- u32 tx_int_coal;
+ struct mib_counters mib_counters;
+ struct work_struct tx_timeout_task;
struct mii_if_info mii;
/*
int default_rx_ring_size;
unsigned long rx_desc_sram_addr;
int rx_desc_sram_size;
+ u8 rxq_mask;
+ int rxq_primary;
struct napi_struct napi;
- struct rx_queue rxq[1];
+ struct rx_queue rxq[8];
+
+ /*
+ * TX state.
+ */
+ int default_tx_ring_size;
+ unsigned long tx_desc_sram_addr;
+ int tx_desc_sram_size;
+ u8 txq_mask;
+ int txq_primary;
+ struct tx_queue txq[8];
+#ifdef MV643XX_ETH_TX_FAST_REFILL
+ int tx_clean_threshold;
+#endif
};
/* rxq/txq helper functions *************************************************/
static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
{
- return container_of(rxq, struct mv643xx_eth_private, rxq[0]);
+ return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
+}
+
+static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
+{
+ return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
}
static void rxq_enable(struct rx_queue *rxq)
{
struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
- wrl(mp, RXQ_COMMAND(mp->port_num), 1);
+ wrl(mp, RXQ_COMMAND(mp->port_num), 1 << rxq->index);
}
static void rxq_disable(struct rx_queue *rxq)
{
struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
- u8 mask = 1;
+ u8 mask = 1 << rxq->index;
wrl(mp, RXQ_COMMAND(mp->port_num), mask << 8);
while (rdl(mp, RXQ_COMMAND(mp->port_num)) & mask)
udelay(10);
}
-static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
- unsigned int queues)
+static void txq_enable(struct tx_queue *txq)
{
- wrl(mp, TXQ_COMMAND(mp->port_num), queues);
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ wrl(mp, TXQ_COMMAND(mp->port_num), 1 << txq->index);
}
-static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
+static void txq_disable(struct tx_queue *txq)
{
- unsigned int port_num = mp->port_num;
- u32 queues;
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ u8 mask = 1 << txq->index;
- /* Stop Tx port activity. Check port Tx activity. */
- queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
- if (queues) {
- /* Issue stop command for active queues only */
- wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
+ wrl(mp, TXQ_COMMAND(mp->port_num), mask << 8);
+ while (rdl(mp, TXQ_COMMAND(mp->port_num)) & mask)
+ udelay(10);
+}
- /* Wait for all Tx activity to terminate. */
- /* Check port cause register that all Tx queues are stopped */
- while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
- udelay(10);
+static void __txq_maybe_wake(struct tx_queue *txq)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
- /* Wait for Tx FIFO to empty */
- while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
- udelay(10);
- }
+ /*
+ * netif_{stop,wake}_queue() flow control only applies to
+ * the primary queue.
+ */
+ BUG_ON(txq->index != mp->txq_primary);
- return queues;
+ if (txq->tx_ring_size - txq->tx_desc_count >= MAX_DESCS_PER_SKB)
+ netif_wake_queue(mp->dev);
}
/* rx ***********************************************************************/
-static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
+static void txq_reclaim(struct tx_queue *txq, int force);
static void rxq_refill(struct rx_queue *rxq)
{
RX_ENABLE_INTERRUPT;
wmb();
- skb_reserve(skb, ETH_HW_IP_ALIGN);
+ /*
+ * The hardware automatically prepends 2 bytes of
+ * dummy data to each received packet, so that the
+ * IP header ends up 16-byte aligned.
+ */
+ skb_reserve(skb, 2);
}
- if (rxq->rx_desc_count == 0) {
+ if (rxq->rx_desc_count != rxq->rx_ring_size) {
rxq->rx_oom.expires = jiffies + (HZ / 10);
add_timer(&rxq->rx_oom);
}
rx = 0;
while (rx < budget) {
- struct sk_buff *skb;
- volatile struct rx_desc *rx_desc;
+ struct rx_desc *rx_desc;
unsigned int cmd_sts;
+ struct sk_buff *skb;
unsigned long flags;
spin_lock_irqsave(&mp->lock, flags);
spin_unlock_irqrestore(&mp->lock, flags);
- dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN,
- mp->dev->mtu + 24, DMA_FROM_DEVICE);
+ dma_unmap_single(NULL, rx_desc->buf_ptr + 2,
+ mp->dev->mtu + 24, DMA_FROM_DEVICE);
rxq->rx_desc_count--;
rx++;
/*
* Update statistics.
- * Note byte count includes 4 byte CRC count
+ *
+ * Note that the descriptor byte count includes 2 dummy
+ * bytes automatically inserted by the hardware at the
+ * start of the packet (which we don't count), and a 4
+ * byte CRC at the end of the packet (which we do count).
*/
stats->rx_packets++;
- stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
+ stats->rx_bytes += rx_desc->byte_cnt - 2;
/*
- * In case received a packet without first / last bits on OR
- * the error summary bit is on, the packets needs to be dropeed.
+ * In case we received a packet without first / last bits
+ * on, or the error summary bit is set, the packet needs
+ * to be dropped.
*/
if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
(RX_FIRST_DESC | RX_LAST_DESC))
|| (cmd_sts & ERROR_SUMMARY)) {
stats->rx_dropped++;
+
if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
(RX_FIRST_DESC | RX_LAST_DESC)) {
if (net_ratelimit())
- printk(KERN_ERR
- "%s: Received packet spread "
- "on multiple descriptors\n",
- mp->dev->name);
+ dev_printk(KERN_ERR, &mp->dev->dev,
+ "received packet spanning "
+ "multiple descriptors\n");
}
+
if (cmd_sts & ERROR_SUMMARY)
stats->rx_errors++;
* The -4 is for the CRC in the trailer of the
* received packet
*/
- skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4);
+ skb_put(skb, rx_desc->byte_cnt - 2 - 4);
if (cmd_sts & LAYER_4_CHECKSUM_OK) {
skb->ip_summed = CHECKSUM_UNNECESSARY;
netif_rx(skb);
#endif
}
+
mp->dev->last_rx = jiffies;
}
+
rxq_refill(rxq);
return rx;
{
struct mv643xx_eth_private *mp;
int rx;
+ int i;
mp = container_of(napi, struct mv643xx_eth_private, napi);
#ifdef MV643XX_ETH_TX_FAST_REFILL
if (++mp->tx_clean_threshold > 5) {
- mv643xx_eth_free_completed_tx_descs(mp->dev);
mp->tx_clean_threshold = 0;
+ for (i = 0; i < 8; i++)
+ if (mp->txq_mask & (1 << i))
+ txq_reclaim(mp->txq + i, 0);
}
#endif
- rx = rxq_process(mp->rxq, budget);
+ rx = 0;
+ for (i = 7; rx < budget && i >= 0; i--)
+ if (mp->rxq_mask & (1 << i))
+ rx += rxq_process(mp->rxq + i, budget - rx);
if (rx < budget) {
netif_rx_complete(mp->dev, napi);
wrl(mp, INT_CAUSE(mp->port_num), 0);
wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
- wrl(mp, INT_MASK(mp->port_num), INT_RX | INT_EXT);
+ wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
}
return rx;
/* tx ***********************************************************************/
static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
{
- unsigned int frag;
- skb_frag_t *fragp;
+ int frag;
for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
- fragp = &skb_shinfo(skb)->frags[frag];
- if (fragp->size <= 8 && fragp->page_offset & 0x7)
+ skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
+ if (fragp->size <= 8 && fragp->page_offset & 7)
return 1;
}
+
return 0;
}
-static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
+static int txq_alloc_desc_index(struct tx_queue *txq)
{
int tx_desc_curr;
- BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
+ BUG_ON(txq->tx_desc_count >= txq->tx_ring_size);
- tx_desc_curr = mp->tx_curr_desc;
- mp->tx_curr_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
+ tx_desc_curr = txq->tx_curr_desc;
+ txq->tx_curr_desc = (tx_desc_curr + 1) % txq->tx_ring_size;
- BUG_ON(mp->tx_curr_desc == mp->tx_used_desc);
+ BUG_ON(txq->tx_curr_desc == txq->tx_used_desc);
return tx_desc_curr;
}
-static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
- struct sk_buff *skb)
+static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
{
+ int nr_frags = skb_shinfo(skb)->nr_frags;
int frag;
- int tx_index;
- struct tx_desc *desc;
- for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
- skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
-
- tx_index = alloc_tx_desc_index(mp);
- desc = &mp->tx_desc_area[tx_index];
-
- desc->cmd_sts = BUFFER_OWNED_BY_DMA;
- /* Last Frag enables interrupt and frees the skb */
- if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
- desc->cmd_sts |= ZERO_PADDING |
- TX_LAST_DESC |
- TX_ENABLE_INTERRUPT;
- mp->tx_skb[tx_index] = skb;
- } else
- mp->tx_skb[tx_index] = NULL;
-
- desc = &mp->tx_desc_area[tx_index];
+ for (frag = 0; frag < nr_frags; frag++) {
+ skb_frag_t *this_frag;
+ int tx_index;
+ struct tx_desc *desc;
+
+ this_frag = &skb_shinfo(skb)->frags[frag];
+ tx_index = txq_alloc_desc_index(txq);
+ desc = &txq->tx_desc_area[tx_index];
+
+ /*
+ * The last fragment will generate an interrupt
+ * which will free the skb on TX completion.
+ */
+ if (frag == nr_frags - 1) {
+ desc->cmd_sts = BUFFER_OWNED_BY_DMA |
+ ZERO_PADDING | TX_LAST_DESC |
+ TX_ENABLE_INTERRUPT;
+ txq->tx_skb[tx_index] = skb;
+ } else {
+ desc->cmd_sts = BUFFER_OWNED_BY_DMA;
+ txq->tx_skb[tx_index] = NULL;
+ }
+
desc->l4i_chk = 0;
desc->byte_cnt = this_frag->size;
desc->buf_ptr = dma_map_page(NULL, this_frag->page,
return (__force __be16)sum;
}
-static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
- struct sk_buff *skb)
+static void txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
{
+ int nr_frags = skb_shinfo(skb)->nr_frags;
int tx_index;
struct tx_desc *desc;
u32 cmd_sts;
int length;
- int nr_frags = skb_shinfo(skb)->nr_frags;
cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
- tx_index = alloc_tx_desc_index(mp);
- desc = &mp->tx_desc_area[tx_index];
+ tx_index = txq_alloc_desc_index(txq);
+ desc = &txq->tx_desc_area[tx_index];
if (nr_frags) {
- tx_fill_frag_descs(mp, skb);
+ txq_submit_frag_skb(txq, skb);
length = skb_headlen(skb);
- mp->tx_skb[tx_index] = NULL;
+ txq->tx_skb[tx_index] = NULL;
} else {
cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
length = skb->len;
- mp->tx_skb[tx_index] = skb;
+ txq->tx_skb[tx_index] = skb;
}
desc->byte_cnt = length;
/* ensure all descriptors are written before poking hardware */
wmb();
- mv643xx_eth_port_enable_tx(mp, 1);
+ txq_enable(txq);
- mp->tx_desc_count += nr_frags + 1;
+ txq->tx_desc_count += nr_frags + 1;
}
-static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
+static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
struct net_device_stats *stats = &dev->stats;
+ struct tx_queue *txq;
unsigned long flags;
- BUG_ON(netif_queue_stopped(dev));
-
if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
stats->tx_dropped++;
- printk(KERN_DEBUG "%s: failed to linearize tiny "
- "unaligned fragment\n", dev->name);
+ dev_printk(KERN_DEBUG, &dev->dev,
+ "failed to linearize skb with tiny "
+ "unaligned fragment\n");
return NETDEV_TX_BUSY;
}
spin_lock_irqsave(&mp->lock, flags);
- if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
- printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
- netif_stop_queue(dev);
+ txq = mp->txq + mp->txq_primary;
+
+ if (txq->tx_ring_size - txq->tx_desc_count < MAX_DESCS_PER_SKB) {
spin_unlock_irqrestore(&mp->lock, flags);
- return NETDEV_TX_BUSY;
+ if (txq->index == mp->txq_primary && net_ratelimit())
+ dev_printk(KERN_ERR, &dev->dev,
+ "primary tx queue full?!\n");
+ kfree_skb(skb);
+ return NETDEV_TX_OK;
}
- tx_submit_descs_for_skb(mp, skb);
+ txq_submit_skb(txq, skb);
stats->tx_bytes += skb->len;
stats->tx_packets++;
dev->trans_start = jiffies;
- if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
- netif_stop_queue(dev);
+ if (txq->index == mp->txq_primary) {
+ int entries_left;
+
+ entries_left = txq->tx_ring_size - txq->tx_desc_count;
+ if (entries_left < MAX_DESCS_PER_SKB)
+ netif_stop_queue(dev);
+ }
spin_unlock_irqrestore(&mp->lock, flags);
}
+/* tx rate control **********************************************************/
+/*
+ * Set total maximum TX rate (shared by all TX queues for this port)
+ * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
+ */
+static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
+{
+ int token_rate;
+ int mtu;
+ int bucket_size;
+
+ token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
+ if (token_rate > 1023)
+ token_rate = 1023;
+
+ mtu = (mp->dev->mtu + 255) >> 8;
+ if (mtu > 63)
+ mtu = 63;
+
+ bucket_size = (burst + 255) >> 8;
+ if (bucket_size > 65535)
+ bucket_size = 65535;
+
+ if (mp->shared->tx_bw_control_moved) {
+ wrl(mp, TX_BW_RATE_MOVED(mp->port_num), token_rate);
+ wrl(mp, TX_BW_MTU_MOVED(mp->port_num), mtu);
+ wrl(mp, TX_BW_BURST_MOVED(mp->port_num), bucket_size);
+ } else {
+ wrl(mp, TX_BW_RATE(mp->port_num), token_rate);
+ wrl(mp, TX_BW_MTU(mp->port_num), mtu);
+ wrl(mp, TX_BW_BURST(mp->port_num), bucket_size);
+ }
+}
+
+static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int token_rate;
+ int bucket_size;
+
+ token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
+ if (token_rate > 1023)
+ token_rate = 1023;
+
+ bucket_size = (burst + 255) >> 8;
+ if (bucket_size > 65535)
+ bucket_size = 65535;
+
+ wrl(mp, TXQ_BW_TOKENS(mp->port_num, txq->index), token_rate << 14);
+ wrl(mp, TXQ_BW_CONF(mp->port_num, txq->index),
+ (bucket_size << 10) | token_rate);
+}
+
+static void txq_set_fixed_prio_mode(struct tx_queue *txq)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int off;
+ u32 val;
+
+ /*
+ * Turn on fixed priority mode.
+ */
+ if (mp->shared->tx_bw_control_moved)
+ off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
+ else
+ off = TXQ_FIX_PRIO_CONF(mp->port_num);
+
+ val = rdl(mp, off);
+ val |= 1 << txq->index;
+ wrl(mp, off, val);
+}
+
+static void txq_set_wrr(struct tx_queue *txq, int weight)
+{
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
+ int off;
+ u32 val;
+
+ /*
+ * Turn off fixed priority mode.
+ */
+ if (mp->shared->tx_bw_control_moved)
+ off = TXQ_FIX_PRIO_CONF_MOVED(mp->port_num);
+ else
+ off = TXQ_FIX_PRIO_CONF(mp->port_num);
+
+ val = rdl(mp, off);
+ val &= ~(1 << txq->index);
+ wrl(mp, off, val);
+
+ /*
+ * Configure WRR weight for this queue.
+ */
+ off = TXQ_BW_WRR_CONF(mp->port_num, txq->index);
+
+ val = rdl(mp, off);
+ val = (val & ~0xff) | (weight & 0xff);
+ wrl(mp, off, val);
+}
+
+
/* mii management interface *************************************************/
-static int phy_addr_get(struct mv643xx_eth_private *mp);
+#define SMI_BUSY 0x10000000
+#define SMI_READ_VALID 0x08000000
+#define SMI_OPCODE_READ 0x04000000
+#define SMI_OPCODE_WRITE 0x00000000
-static void read_smi_reg(struct mv643xx_eth_private *mp,
- unsigned int phy_reg, unsigned int *value)
+static void smi_reg_read(struct mv643xx_eth_private *mp, unsigned int addr,
+ unsigned int reg, unsigned int *value)
{
void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
- int phy_addr = phy_addr_get(mp);
unsigned long flags;
int i;
udelay(10);
}
- writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
+ writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
/* now wait for the data to be valid */
for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
}
-static void write_smi_reg(struct mv643xx_eth_private *mp,
- unsigned int phy_reg, unsigned int value)
+static void smi_reg_write(struct mv643xx_eth_private *mp,
+ unsigned int addr,
+ unsigned int reg, unsigned int value)
{
void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
- int phy_addr = phy_addr_get(mp);
unsigned long flags;
int i;
udelay(10);
}
- writel((phy_addr << 16) | (phy_reg << 21) |
- SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
+ writel(SMI_OPCODE_WRITE | (reg << 21) |
+ (addr << 16) | (value & 0xffff), smi_reg);
out:
spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
}
/* mib counters *************************************************************/
-static void clear_mib_counters(struct mv643xx_eth_private *mp)
+static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
{
- unsigned int port_num = mp->port_num;
- int i;
-
- /* Perform dummy reads from MIB counters */
- for (i = 0; i < 0x80; i += 4)
- rdl(mp, MIB_COUNTERS(port_num) + i);
+ return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
}
-static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
+static void mib_counters_clear(struct mv643xx_eth_private *mp)
{
- return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
+ int i;
+
+ for (i = 0; i < 0x80; i += 4)
+ mib_read(mp, i);
}
-static void update_mib_counters(struct mv643xx_eth_private *mp)
+static void mib_counters_update(struct mv643xx_eth_private *mp)
{
struct mib_counters *p = &mp->mib_counters;
- p->good_octets_received += read_mib(mp, 0x00);
- p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
- p->bad_octets_received += read_mib(mp, 0x08);
- p->internal_mac_transmit_err += read_mib(mp, 0x0c);
- p->good_frames_received += read_mib(mp, 0x10);
- p->bad_frames_received += read_mib(mp, 0x14);
- p->broadcast_frames_received += read_mib(mp, 0x18);
- p->multicast_frames_received += read_mib(mp, 0x1c);
- p->frames_64_octets += read_mib(mp, 0x20);
- p->frames_65_to_127_octets += read_mib(mp, 0x24);
- p->frames_128_to_255_octets += read_mib(mp, 0x28);
- p->frames_256_to_511_octets += read_mib(mp, 0x2c);
- p->frames_512_to_1023_octets += read_mib(mp, 0x30);
- p->frames_1024_to_max_octets += read_mib(mp, 0x34);
- p->good_octets_sent += read_mib(mp, 0x38);
- p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
- p->good_frames_sent += read_mib(mp, 0x40);
- p->excessive_collision += read_mib(mp, 0x44);
- p->multicast_frames_sent += read_mib(mp, 0x48);
- p->broadcast_frames_sent += read_mib(mp, 0x4c);
- p->unrec_mac_control_received += read_mib(mp, 0x50);
- p->fc_sent += read_mib(mp, 0x54);
- p->good_fc_received += read_mib(mp, 0x58);
- p->bad_fc_received += read_mib(mp, 0x5c);
- p->undersize_received += read_mib(mp, 0x60);
- p->fragments_received += read_mib(mp, 0x64);
- p->oversize_received += read_mib(mp, 0x68);
- p->jabber_received += read_mib(mp, 0x6c);
- p->mac_receive_error += read_mib(mp, 0x70);
- p->bad_crc_event += read_mib(mp, 0x74);
- p->collision += read_mib(mp, 0x78);
- p->late_collision += read_mib(mp, 0x7c);
+ p->good_octets_received += mib_read(mp, 0x00);
+ p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
+ p->bad_octets_received += mib_read(mp, 0x08);
+ p->internal_mac_transmit_err += mib_read(mp, 0x0c);
+ p->good_frames_received += mib_read(mp, 0x10);
+ p->bad_frames_received += mib_read(mp, 0x14);
+ p->broadcast_frames_received += mib_read(mp, 0x18);
+ p->multicast_frames_received += mib_read(mp, 0x1c);
+ p->frames_64_octets += mib_read(mp, 0x20);
+ p->frames_65_to_127_octets += mib_read(mp, 0x24);
+ p->frames_128_to_255_octets += mib_read(mp, 0x28);
+ p->frames_256_to_511_octets += mib_read(mp, 0x2c);
+ p->frames_512_to_1023_octets += mib_read(mp, 0x30);
+ p->frames_1024_to_max_octets += mib_read(mp, 0x34);
+ p->good_octets_sent += mib_read(mp, 0x38);
+ p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
+ p->good_frames_sent += mib_read(mp, 0x40);
+ p->excessive_collision += mib_read(mp, 0x44);
+ p->multicast_frames_sent += mib_read(mp, 0x48);
+ p->broadcast_frames_sent += mib_read(mp, 0x4c);
+ p->unrec_mac_control_received += mib_read(mp, 0x50);
+ p->fc_sent += mib_read(mp, 0x54);
+ p->good_fc_received += mib_read(mp, 0x58);
+ p->bad_fc_received += mib_read(mp, 0x5c);
+ p->undersize_received += mib_read(mp, 0x60);
+ p->fragments_received += mib_read(mp, 0x64);
+ p->oversize_received += mib_read(mp, 0x68);
+ p->jabber_received += mib_read(mp, 0x6c);
+ p->mac_receive_error += mib_read(mp, 0x70);
+ p->bad_crc_event += mib_read(mp, 0x74);
+ p->collision += mib_read(mp, 0x78);
+ p->late_collision += mib_read(mp, 0x7c);
}
err = mii_ethtool_gset(&mp->mii, cmd);
spin_unlock_irq(&mp->lock);
- /* The PHY may support 1000baseT_Half, but the mv643xx does not */
+ /*
+ * The MAC does not support 1000baseT_Half.
+ */
cmd->supported &= ~SUPPORTED_1000baseT_Half;
cmd->advertising &= ~ADVERTISED_1000baseT_Half;
return err;
}
+static int mv643xx_eth_get_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ cmd->supported = SUPPORTED_MII;
+ cmd->advertising = ADVERTISED_MII;
+ cmd->speed = SPEED_1000;
+ cmd->duplex = DUPLEX_FULL;
+ cmd->port = PORT_MII;
+ cmd->phy_address = 0;
+ cmd->transceiver = XCVR_INTERNAL;
+ cmd->autoneg = AUTONEG_DISABLE;
+ cmd->maxtxpkt = 1;
+ cmd->maxrxpkt = 1;
+
+ return 0;
+}
+
static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
int err;
+ /*
+ * The MAC does not support 1000baseT_Half.
+ */
+ cmd->advertising &= ~ADVERTISED_1000baseT_Half;
+
spin_lock_irq(&mp->lock);
err = mii_ethtool_sset(&mp->mii, cmd);
spin_unlock_irq(&mp->lock);
return err;
}
-static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
- struct ethtool_drvinfo *drvinfo)
+static int mv643xx_eth_set_settings_phyless(struct net_device *dev, struct ethtool_cmd *cmd)
+{
+ return -EINVAL;
+}
+
+static void mv643xx_eth_get_drvinfo(struct net_device *dev,
+ struct ethtool_drvinfo *drvinfo)
{
strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
strncpy(drvinfo->fw_version, "N/A", 32);
- strncpy(drvinfo->bus_info, "mv643xx", 32);
+ strncpy(drvinfo->bus_info, "platform", 32);
drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
}
-static int mv643xx_eth_nway_restart(struct net_device *dev)
+static int mv643xx_eth_nway_reset(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
return mii_nway_restart(&mp->mii);
}
+static int mv643xx_eth_nway_reset_phyless(struct net_device *dev)
+{
+ return -EINVAL;
+}
+
static u32 mv643xx_eth_get_link(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
return mii_link_ok(&mp->mii);
}
-static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
- uint8_t *data)
+static u32 mv643xx_eth_get_link_phyless(struct net_device *dev)
+{
+ return 1;
+}
+
+static void mv643xx_eth_get_strings(struct net_device *dev,
+ uint32_t stringset, uint8_t *data)
{
int i;
- switch(stringset) {
- case ETH_SS_STATS:
- for (i=0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
+ if (stringset == ETH_SS_STATS) {
+ for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
memcpy(data + i * ETH_GSTRING_LEN,
mv643xx_eth_stats[i].stat_string,
ETH_GSTRING_LEN);
}
- break;
}
}
-static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
- struct ethtool_stats *stats, uint64_t *data)
+static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
+ struct ethtool_stats *stats,
+ uint64_t *data)
{
- struct mv643xx_eth_private *mp = netdev->priv;
+ struct mv643xx_eth_private *mp = dev->priv;
int i;
- update_mib_counters(mp);
+ mib_counters_update(mp);
for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
const struct mv643xx_eth_stats *stat;
}
}
-static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
+static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
{
- switch (sset) {
- case ETH_SS_STATS:
+ if (sset == ETH_SS_STATS)
return ARRAY_SIZE(mv643xx_eth_stats);
- default:
- return -EOPNOTSUPP;
- }
+
+ return -EOPNOTSUPP;
}
static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
- .get_settings = mv643xx_eth_get_settings,
- .set_settings = mv643xx_eth_set_settings,
- .get_drvinfo = mv643xx_eth_get_drvinfo,
- .get_link = mv643xx_eth_get_link,
+ .get_settings = mv643xx_eth_get_settings,
+ .set_settings = mv643xx_eth_set_settings,
+ .get_drvinfo = mv643xx_eth_get_drvinfo,
+ .nway_reset = mv643xx_eth_nway_reset,
+ .get_link = mv643xx_eth_get_link,
+ .set_sg = ethtool_op_set_sg,
+ .get_strings = mv643xx_eth_get_strings,
+ .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
+ .get_sset_count = mv643xx_eth_get_sset_count,
+};
+
+static const struct ethtool_ops mv643xx_eth_ethtool_ops_phyless = {
+ .get_settings = mv643xx_eth_get_settings_phyless,
+ .set_settings = mv643xx_eth_set_settings_phyless,
+ .get_drvinfo = mv643xx_eth_get_drvinfo,
+ .nway_reset = mv643xx_eth_nway_reset_phyless,
+ .get_link = mv643xx_eth_get_link_phyless,
.set_sg = ethtool_op_set_sg,
+ .get_strings = mv643xx_eth_get_strings,
+ .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
.get_sset_count = mv643xx_eth_get_sset_count,
- .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
- .get_strings = mv643xx_eth_get_strings,
- .nway_reset = mv643xx_eth_nway_restart,
};
/* address handling *********************************************************/
static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
{
- unsigned int port_num = mp->port_num;
unsigned int mac_h;
unsigned int mac_l;
- mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
- mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
+ mac_h = rdl(mp, MAC_ADDR_HIGH(mp->port_num));
+ mac_l = rdl(mp, MAC_ADDR_LOW(mp->port_num));
addr[0] = (mac_h >> 24) & 0xff;
addr[1] = (mac_h >> 16) & 0xff;
static void init_mac_tables(struct mv643xx_eth_private *mp)
{
- unsigned int port_num = mp->port_num;
- int table_index;
-
- /* Clear DA filter unicast table (Ex_dFUT) */
- for (table_index = 0; table_index <= 0xC; table_index += 4)
- wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
+ int i;
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
+ for (i = 0; i < 0x100; i += 4) {
+ wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
+ wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
}
+
+ for (i = 0; i < 0x10; i += 4)
+ wrl(mp, UNICAST_TABLE(mp->port_num) + i, 0);
}
static void set_filter_table_entry(struct mv643xx_eth_private *mp,
- int table, unsigned char entry)
+ int table, unsigned char entry)
{
unsigned int table_reg;
- unsigned int tbl_offset;
- unsigned int reg_offset;
-
- tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
- reg_offset = entry % 4; /* Entry offset within the register */
/* Set "accepts frame bit" at specified table entry */
- table_reg = rdl(mp, table + tbl_offset);
- table_reg |= 0x01 << (8 * reg_offset);
- wrl(mp, table + tbl_offset, table_reg);
+ table_reg = rdl(mp, table + (entry & 0xfc));
+ table_reg |= 0x01 << (8 * (entry & 3));
+ wrl(mp, table + (entry & 0xfc), table_reg);
}
static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
{
- unsigned int port_num = mp->port_num;
unsigned int mac_h;
unsigned int mac_l;
int table;
- mac_l = (addr[4] << 8) | (addr[5]);
- mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
- (addr[3] << 0);
+ mac_l = (addr[4] << 8) | addr[5];
+ mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
- wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
- wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
+ wrl(mp, MAC_ADDR_LOW(mp->port_num), mac_l);
+ wrl(mp, MAC_ADDR_HIGH(mp->port_num), mac_h);
- /* Accept frames with this address */
- table = UNICAST_TABLE(port_num);
+ table = UNICAST_TABLE(mp->port_num);
set_filter_table_entry(mp, table, addr[5] & 0x0f);
}
-static void mv643xx_eth_update_mac_address(struct net_device *dev)
+static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
+ /* +2 is for the offset of the HW addr type */
+ memcpy(dev->dev_addr, addr + 2, 6);
+
init_mac_tables(mp);
uc_addr_set(mp, dev->dev_addr);
-}
-
-static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
-{
- int i;
- for (i = 0; i < 6; i++)
- /* +2 is for the offset of the HW addr type */
- dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
- mv643xx_eth_update_mac_address(dev);
return 0;
}
return crc;
}
-static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr)
+static void mv643xx_eth_set_rx_mode(struct net_device *dev)
{
- unsigned int port_num = mp->port_num;
- int table;
- int crc;
-
- if ((addr[0] == 0x01) && (addr[1] == 0x00) &&
- (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) {
- table = SPECIAL_MCAST_TABLE(port_num);
- set_filter_table_entry(mp, table, addr[5]);
- return;
- }
-
- crc = addr_crc(addr);
-
- table = OTHER_MCAST_TABLE(port_num);
- set_filter_table_entry(mp, table, crc);
-}
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+ u32 port_config;
+ struct dev_addr_list *addr;
+ int i;
-static void set_multicast_list(struct net_device *dev)
-{
+ port_config = rdl(mp, PORT_CONFIG(mp->port_num));
+ if (dev->flags & IFF_PROMISC)
+ port_config |= UNICAST_PROMISCUOUS_MODE;
+ else
+ port_config &= ~UNICAST_PROMISCUOUS_MODE;
+ wrl(mp, PORT_CONFIG(mp->port_num), port_config);
- struct dev_mc_list *mc_list;
- int i;
- int table_index;
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
+ if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
+ int port_num = mp->port_num;
+ u32 accept = 0x01010101;
- /* If the device is in promiscuous mode or in all multicast mode,
- * we will fully populate both multicast tables with accept.
- * This is guaranteed to yield a match on all multicast addresses...
- */
- if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Set all entries in DA filter special multicast
- * table (Ex_dFSMT)
- * Set for ETH_Q0 for now
- * Bits
- * 0 Accept=1, Drop=0
- * 3-1 Queue ETH_Q0=0
- * 7-4 Reserved = 0;
- */
- wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
-
- /* Set all entries in DA filter other multicast
- * table (Ex_dFOMT)
- * Set for ETH_Q0 for now
- * Bits
- * 0 Accept=1, Drop=0
- * 3-1 Queue ETH_Q0=0
- * 7-4 Reserved = 0;
- */
- wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
+ for (i = 0; i < 0x100; i += 4) {
+ wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
+ wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
}
return;
}
- /* We will clear out multicast tables every time we get the list.
- * Then add the entire new list...
- */
- for (table_index = 0; table_index <= 0xFC; table_index += 4) {
- /* Clear DA filter special multicast table (Ex_dFSMT) */
- wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
-
- /* Clear DA filter other multicast table (Ex_dFOMT) */
- wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
+ for (i = 0; i < 0x100; i += 4) {
+ wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, 0);
+ wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, 0);
}
- /* Get pointer to net_device multicast list and add each one... */
- for (i = 0, mc_list = dev->mc_list;
- (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
- i++, mc_list = mc_list->next)
- if (mc_list->dmi_addrlen == 6)
- mc_addr(mp, mc_list->dmi_addr);
-}
+ for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
+ u8 *a = addr->da_addr;
+ int table;
-static void mv643xx_eth_set_rx_mode(struct net_device *dev)
-{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- u32 config_reg;
+ if (addr->da_addrlen != 6)
+ continue;
- config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
- if (dev->flags & IFF_PROMISC)
- config_reg |= UNICAST_PROMISCUOUS_MODE;
- else
- config_reg &= ~UNICAST_PROMISCUOUS_MODE;
- wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
+ if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
+ table = SPECIAL_MCAST_TABLE(mp->port_num);
+ set_filter_table_entry(mp, table, a[5]);
+ } else {
+ int crc = addr_crc(a);
- set_multicast_list(dev);
+ table = OTHER_MCAST_TABLE(mp->port_num);
+ set_filter_table_entry(mp, table, crc);
+ }
+ }
}
/* rx/tx queue initialisation ***********************************************/
-static int rxq_init(struct mv643xx_eth_private *mp)
+static int rxq_init(struct mv643xx_eth_private *mp, int index)
{
- struct rx_queue *rxq = mp->rxq;
+ struct rx_queue *rxq = mp->rxq + index;
struct rx_desc *rx_desc;
int size;
int i;
+ rxq->index = index;
+
rxq->rx_ring_size = mp->default_rx_ring_size;
rxq->rx_desc_count = 0;
size = rxq->rx_ring_size * sizeof(struct rx_desc);
- if (size <= mp->rx_desc_sram_size) {
+ if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size) {
rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
mp->rx_desc_sram_size);
rxq->rx_desc_dma = mp->rx_desc_sram_addr;
out_free:
- if (size <= mp->rx_desc_sram_size)
+ if (index == mp->rxq_primary && size <= mp->rx_desc_sram_size)
iounmap(rxq->rx_desc_area);
else
dma_free_coherent(NULL, size,
rxq->rx_desc_count);
}
- if (rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
+ if (rxq->index == mp->rxq_primary &&
+ rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
iounmap(rxq->rx_desc_area);
else
dma_free_coherent(NULL, rxq->rx_desc_area_size,
kfree(rxq->rx_skb);
}
-static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
+static int txq_init(struct mv643xx_eth_private *mp, int index)
{
- int tx_desc_num = mp->tx_ring_size;
- struct tx_desc *p_tx_desc;
+ struct tx_queue *txq = mp->txq + index;
+ struct tx_desc *tx_desc;
+ int size;
int i;
- /* Initialize the next_desc_ptr links in the Tx descriptors ring */
- p_tx_desc = (struct tx_desc *)mp->tx_desc_area;
- for (i = 0; i < tx_desc_num; i++) {
- p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
- ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
+ txq->index = index;
+
+ txq->tx_ring_size = mp->default_tx_ring_size;
+
+ txq->tx_desc_count = 0;
+ txq->tx_curr_desc = 0;
+ txq->tx_used_desc = 0;
+
+ size = txq->tx_ring_size * sizeof(struct tx_desc);
+
+ if (index == mp->txq_primary && size <= mp->tx_desc_sram_size) {
+ txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
+ mp->tx_desc_sram_size);
+ txq->tx_desc_dma = mp->tx_desc_sram_addr;
+ } else {
+ txq->tx_desc_area = dma_alloc_coherent(NULL, size,
+ &txq->tx_desc_dma,
+ GFP_KERNEL);
+ }
+
+ if (txq->tx_desc_area == NULL) {
+ dev_printk(KERN_ERR, &mp->dev->dev,
+ "can't allocate tx ring (%d bytes)\n", size);
+ goto out;
+ }
+ memset(txq->tx_desc_area, 0, size);
+
+ txq->tx_desc_area_size = size;
+ txq->tx_skb = kmalloc(txq->tx_ring_size * sizeof(*txq->tx_skb),
+ GFP_KERNEL);
+ if (txq->tx_skb == NULL) {
+ dev_printk(KERN_ERR, &mp->dev->dev,
+ "can't allocate tx skb ring\n");
+ goto out_free;
+ }
+
+ tx_desc = (struct tx_desc *)txq->tx_desc_area;
+ for (i = 0; i < txq->tx_ring_size; i++) {
+ int nexti = (i + 1) % txq->tx_ring_size;
+ tx_desc[i].next_desc_ptr = txq->tx_desc_dma +
+ nexti * sizeof(struct tx_desc);
}
- mp->tx_curr_desc = 0;
- mp->tx_used_desc = 0;
+ return 0;
+
+
+out_free:
+ if (index == mp->txq_primary && size <= mp->tx_desc_sram_size)
+ iounmap(txq->tx_desc_area);
+ else
+ dma_free_coherent(NULL, size,
+ txq->tx_desc_area,
+ txq->tx_desc_dma);
- mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
+out:
+ return -ENOMEM;
}
-static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
+static void txq_reclaim(struct tx_queue *txq, int force)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- struct tx_desc *desc;
- u32 cmd_sts;
- struct sk_buff *skb;
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
unsigned long flags;
- int tx_index;
- dma_addr_t addr;
- int count;
- int released = 0;
-
- while (mp->tx_desc_count > 0) {
- spin_lock_irqsave(&mp->lock, flags);
- /* tx_desc_count might have changed before acquiring the lock */
- if (mp->tx_desc_count <= 0) {
- spin_unlock_irqrestore(&mp->lock, flags);
- return released;
- }
+ spin_lock_irqsave(&mp->lock, flags);
+ while (txq->tx_desc_count > 0) {
+ int tx_index;
+ struct tx_desc *desc;
+ u32 cmd_sts;
+ struct sk_buff *skb;
+ dma_addr_t addr;
+ int count;
- tx_index = mp->tx_used_desc;
- desc = &mp->tx_desc_area[tx_index];
+ tx_index = txq->tx_used_desc;
+ desc = &txq->tx_desc_area[tx_index];
cmd_sts = desc->cmd_sts;
- if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
- spin_unlock_irqrestore(&mp->lock, flags);
- return released;
- }
+ if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA))
+ break;
- mp->tx_used_desc = (tx_index + 1) % mp->tx_ring_size;
- mp->tx_desc_count--;
+ txq->tx_used_desc = (tx_index + 1) % txq->tx_ring_size;
+ txq->tx_desc_count--;
addr = desc->buf_ptr;
count = desc->byte_cnt;
- skb = mp->tx_skb[tx_index];
- if (skb)
- mp->tx_skb[tx_index] = NULL;
+ skb = txq->tx_skb[tx_index];
+ txq->tx_skb[tx_index] = NULL;
if (cmd_sts & ERROR_SUMMARY) {
- printk("%s: Error in TX\n", dev->name);
- dev->stats.tx_errors++;
+ dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
+ mp->dev->stats.tx_errors++;
}
+ /*
+ * Drop mp->lock while we free the skb.
+ */
spin_unlock_irqrestore(&mp->lock, flags);
if (cmd_sts & TX_FIRST_DESC)
if (skb)
dev_kfree_skb_irq(skb);
- released = 1;
+ spin_lock_irqsave(&mp->lock, flags);
}
-
- return released;
-}
-
-static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
-{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
-
- if (mv643xx_eth_free_tx_descs(dev, 0) &&
- mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
- netif_wake_queue(dev);
-}
-
-static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
-{
- mv643xx_eth_free_tx_descs(dev, 1);
+ spin_unlock_irqrestore(&mp->lock, flags);
}
-static void mv643xx_eth_free_tx_rings(struct net_device *dev)
+static void txq_deinit(struct tx_queue *txq)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
-
- /* Stop Tx Queues */
- mv643xx_eth_port_disable_tx(mp);
+ struct mv643xx_eth_private *mp = txq_to_mp(txq);
- /* Free outstanding skb's on TX ring */
- mv643xx_eth_free_all_tx_descs(dev);
+ txq_disable(txq);
+ txq_reclaim(txq, 1);
- BUG_ON(mp->tx_used_desc != mp->tx_curr_desc);
+ BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
- /* Free TX ring */
- if (mp->tx_sram_size)
- iounmap(mp->tx_desc_area);
+ if (txq->index == mp->txq_primary &&
+ txq->tx_desc_area_size <= mp->tx_desc_sram_size)
+ iounmap(txq->tx_desc_area);
else
- dma_free_coherent(NULL, mp->tx_desc_area_size,
- mp->tx_desc_area, mp->tx_desc_dma);
+ dma_free_coherent(NULL, txq->tx_desc_area_size,
+ txq->tx_desc_area, txq->tx_desc_dma);
+
+ kfree(txq->tx_skb);
}
/* netdev ops and related ***************************************************/
-static void port_reset(struct mv643xx_eth_private *mp);
-
-static void mv643xx_eth_update_pscr(struct net_device *dev,
- struct ethtool_cmd *ecmd)
+static void update_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- int port_num = mp->port_num;
- u32 o_pscr, n_pscr;
- unsigned int queues;
+ u32 pscr_o;
+ u32 pscr_n;
- o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
- n_pscr = o_pscr;
+ pscr_o = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
/* clear speed, duplex and rx buffer size fields */
- n_pscr &= ~(SET_MII_SPEED_TO_100 |
- SET_GMII_SPEED_TO_1000 |
- SET_FULL_DUPLEX_MODE |
- MAX_RX_PACKET_MASK);
-
- if (ecmd->duplex == DUPLEX_FULL)
- n_pscr |= SET_FULL_DUPLEX_MODE;
-
- if (ecmd->speed == SPEED_1000)
- n_pscr |= SET_GMII_SPEED_TO_1000 |
- MAX_RX_PACKET_9700BYTE;
- else {
- if (ecmd->speed == SPEED_100)
- n_pscr |= SET_MII_SPEED_TO_100;
- n_pscr |= MAX_RX_PACKET_1522BYTE;
+ pscr_n = pscr_o & ~(SET_MII_SPEED_TO_100 |
+ SET_GMII_SPEED_TO_1000 |
+ SET_FULL_DUPLEX_MODE |
+ MAX_RX_PACKET_MASK);
+
+ if (speed == SPEED_1000) {
+ pscr_n |= SET_GMII_SPEED_TO_1000 | MAX_RX_PACKET_9700BYTE;
+ } else {
+ if (speed == SPEED_100)
+ pscr_n |= SET_MII_SPEED_TO_100;
+ pscr_n |= MAX_RX_PACKET_1522BYTE;
}
- if (n_pscr != o_pscr) {
- if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
- wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
+ if (duplex == DUPLEX_FULL)
+ pscr_n |= SET_FULL_DUPLEX_MODE;
+
+ if (pscr_n != pscr_o) {
+ if ((pscr_o & SERIAL_PORT_ENABLE) == 0)
+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
else {
- queues = mv643xx_eth_port_disable_tx(mp);
-
- o_pscr &= ~SERIAL_PORT_ENABLE;
- wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
- wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
- wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
- if (queues)
- mv643xx_eth_port_enable_tx(mp, queues);
+ int i;
+
+ for (i = 0; i < 8; i++)
+ if (mp->txq_mask & (1 << i))
+ txq_disable(mp->txq + i);
+
+ pscr_o &= ~SERIAL_PORT_ENABLE;
+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_o);
+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), pscr_n);
+
+ for (i = 0; i < 8; i++)
+ if (mp->txq_mask & (1 << i))
+ txq_enable(mp->txq + i);
}
}
}
-static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
+static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
{
struct net_device *dev = (struct net_device *)dev_id;
struct mv643xx_eth_private *mp = netdev_priv(dev);
- u32 int_cause, int_cause_ext = 0;
- unsigned int port_num = mp->port_num;
+ u32 int_cause;
+ u32 int_cause_ext;
+ u32 txq_active;
+
+ int_cause = rdl(mp, INT_CAUSE(mp->port_num)) &
+ (INT_TX_END | INT_RX | INT_EXT);
+ if (int_cause == 0)
+ return IRQ_NONE;
- /* Read interrupt cause registers */
- int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
+ int_cause_ext = 0;
if (int_cause & INT_EXT) {
- int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
+ int_cause_ext = rdl(mp, INT_CAUSE_EXT(mp->port_num))
& (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
- wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
+ wrl(mp, INT_CAUSE_EXT(mp->port_num), ~int_cause_ext);
}
- /* PHY status changed */
- if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
- struct ethtool_cmd cmd;
+ if (int_cause_ext & (INT_EXT_PHY | INT_EXT_LINK)) {
+ if (mp->phy_addr == -1 || mii_link_ok(&mp->mii)) {
+ int i;
+
+ if (mp->phy_addr != -1) {
+ struct ethtool_cmd cmd;
+
+ mii_ethtool_gset(&mp->mii, &cmd);
+ update_pscr(mp, cmd.speed, cmd.duplex);
+ }
+
+ for (i = 0; i < 8; i++)
+ if (mp->txq_mask & (1 << i))
+ txq_enable(mp->txq + i);
- if (mii_link_ok(&mp->mii)) {
- mii_ethtool_gset(&mp->mii, &cmd);
- mv643xx_eth_update_pscr(dev, &cmd);
- mv643xx_eth_port_enable_tx(mp, 1);
if (!netif_carrier_ok(dev)) {
netif_carrier_on(dev);
- if (mp->tx_ring_size - mp->tx_desc_count >=
- MAX_DESCS_PER_SKB)
- netif_wake_queue(dev);
+ __txq_maybe_wake(mp->txq + mp->txq_primary);
}
} else if (netif_carrier_ok(dev)) {
netif_stop_queue(dev);
}
}
+ /*
+ * RxBuffer or RxError set for any of the 8 queues?
+ */
#ifdef MV643XX_ETH_NAPI
if (int_cause & INT_RX) {
- /* schedule the NAPI poll routine to maintain port */
- wrl(mp, INT_MASK(port_num), 0x00000000);
-
- /* wait for previous write to complete */
- rdl(mp, INT_MASK(port_num));
+ wrl(mp, INT_MASK(mp->port_num), 0x00000000);
+ rdl(mp, INT_MASK(mp->port_num));
netif_rx_schedule(dev, &mp->napi);
}
#else
- if (int_cause & INT_RX)
- rxq_process(mp->rxq, INT_MAX);
+ if (int_cause & INT_RX) {
+ int i;
+
+ for (i = 7; i >= 0; i--)
+ if (mp->rxq_mask & (1 << i))
+ rxq_process(mp->rxq + i, INT_MAX);
+ }
#endif
- if (int_cause_ext & INT_EXT_TX)
- mv643xx_eth_free_completed_tx_descs(dev);
+
+ txq_active = rdl(mp, TXQ_COMMAND(mp->port_num));
/*
- * If no real interrupt occured, exit.
- * This can happen when using gigE interrupt coalescing mechanism.
+ * TxBuffer or TxError set for any of the 8 queues?
*/
- if ((int_cause == 0x0) && (int_cause_ext == 0x0))
- return IRQ_NONE;
+ if (int_cause_ext & INT_EXT_TX) {
+ int i;
+
+ for (i = 0; i < 8; i++)
+ if (mp->txq_mask & (1 << i))
+ txq_reclaim(mp->txq + i, 0);
+ }
+
+ /*
+ * Any TxEnd interrupts?
+ */
+ if (int_cause & INT_TX_END) {
+ int i;
+
+ wrl(mp, INT_CAUSE(mp->port_num), ~(int_cause & INT_TX_END));
+ for (i = 0; i < 8; i++) {
+ struct tx_queue *txq = mp->txq + i;
+ if (txq->tx_desc_count && !((txq_active >> i) & 1))
+ txq_enable(txq);
+ }
+ }
+
+ /*
+ * Enough space again in the primary TX queue for a full packet?
+ */
+ if (int_cause_ext & INT_EXT_TX) {
+ struct tx_queue *txq = mp->txq + mp->txq_primary;
+ __txq_maybe_wake(txq);
+ }
return IRQ_HANDLED;
}
static void phy_reset(struct mv643xx_eth_private *mp)
{
- unsigned int phy_reg_data;
+ unsigned int data;
- /* Reset the PHY */
- read_smi_reg(mp, 0, &phy_reg_data);
- phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
- write_smi_reg(mp, 0, phy_reg_data);
+ smi_reg_read(mp, mp->phy_addr, 0, &data);
+ data |= 0x8000;
+ smi_reg_write(mp, mp->phy_addr, 0, data);
- /* wait for PHY to come out of reset */
do {
udelay(1);
- read_smi_reg(mp, 0, &phy_reg_data);
- } while (phy_reg_data & 0x8000);
+ smi_reg_read(mp, mp->phy_addr, 0, &data);
+ } while (data & 0x8000);
}
-static void port_start(struct net_device *dev)
+static void port_start(struct mv643xx_eth_private *mp)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
u32 pscr;
- struct ethtool_cmd ethtool_cmd;
int i;
/*
wrl(mp, SDMA_CONFIG(mp->port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
- mv643xx_eth_get_settings(dev, ðtool_cmd);
- phy_reset(mp);
- mv643xx_eth_set_settings(dev, ðtool_cmd);
+ /*
+ * Perform PHY reset, if there is a PHY.
+ */
+ if (mp->phy_addr != -1) {
+ struct ethtool_cmd cmd;
- /* Add the assigned Ethernet address to the port's address table */
- uc_addr_set(mp, dev->dev_addr);
+ mv643xx_eth_get_settings(mp->dev, &cmd);
+ phy_reset(mp);
+ mv643xx_eth_set_settings(mp->dev, &cmd);
+ }
+
+ /*
+ * Configure TX path and queues.
+ */
+ tx_set_rate(mp, 1000000000, 16777216);
+ for (i = 0; i < 8; i++) {
+ struct tx_queue *txq = mp->txq + i;
+ int off = TXQ_CURRENT_DESC_PTR(mp->port_num, i);
+ u32 addr;
+
+ if ((mp->txq_mask & (1 << i)) == 0)
+ continue;
+
+ addr = (u32)txq->tx_desc_dma;
+ addr += txq->tx_curr_desc * sizeof(struct tx_desc);
+ wrl(mp, off, addr);
+
+ txq_set_rate(txq, 1000000000, 16777216);
+ txq_set_fixed_prio_mode(txq);
+ }
+
+ /*
+ * Add configured unicast address to address filter table.
+ */
+ uc_addr_set(mp, mp->dev->dev_addr);
/*
* Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
wrl(mp, PORT_CONFIG_EXT(mp->port_num), 0x00000000);
/*
- * Enable the receive queue.
+ * Enable the receive queues.
*/
- for (i = 0; i < 1; i++) {
- struct rx_queue *rxq = mp->rxq;
- int off = RXQ_CURRENT_DESC_PTR(mp->port_num);
+ for (i = 0; i < 8; i++) {
+ struct rx_queue *rxq = mp->rxq + i;
+ int off = RXQ_CURRENT_DESC_PTR(mp->port_num, i);
u32 addr;
+ if ((mp->rxq_mask & (1 << i)) == 0)
+ continue;
+
addr = (u32)rxq->rx_desc_dma;
addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
wrl(mp, off, addr);
rxq_enable(rxq);
}
-
-
- wrl(mp, TXQ_CURRENT_DESC_PTR(mp->port_num),
- (u32)((struct tx_desc *)mp->tx_desc_dma + mp->tx_curr_desc));
-
- /* Disable port bandwidth limits by clearing MTU register */
- wrl(mp, TX_BW_MTU(mp->port_num), 0);
}
-#ifdef MV643XX_ETH_COAL
-static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
- unsigned int delay)
+static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
{
- unsigned int port_num = mp->port_num;
unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
-
- /* Set RX Coalescing mechanism */
- wrl(mp, SDMA_CONFIG(port_num),
- ((coal & 0x3fff) << 8) |
- (rdl(mp, SDMA_CONFIG(port_num))
- & 0xffc000ff));
-
- return coal;
+ u32 val;
+
+ val = rdl(mp, SDMA_CONFIG(mp->port_num));
+ if (mp->shared->extended_rx_coal_limit) {
+ if (coal > 0xffff)
+ coal = 0xffff;
+ val &= ~0x023fff80;
+ val |= (coal & 0x8000) << 10;
+ val |= (coal & 0x7fff) << 7;
+ } else {
+ if (coal > 0x3fff)
+ coal = 0x3fff;
+ val &= ~0x003fff00;
+ val |= (coal & 0x3fff) << 8;
+ }
+ wrl(mp, SDMA_CONFIG(mp->port_num), val);
}
-#endif
-static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
- unsigned int delay)
+static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int delay)
{
unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
- /* Set TX Coalescing mechanism */
- wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
-
- return coal;
-}
-
-static void port_init(struct mv643xx_eth_private *mp)
-{
- port_reset(mp);
-
- init_mac_tables(mp);
+ if (coal > 0x3fff)
+ coal = 0x3fff;
+ wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), (coal & 0x3fff) << 4);
}
static int mv643xx_eth_open(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
- unsigned int size;
int err;
+ int i;
- /* Clear any pending ethernet port interrupts */
- wrl(mp, INT_CAUSE(port_num), 0);
- wrl(mp, INT_CAUSE_EXT(port_num), 0);
- /* wait for previous write to complete */
- rdl(mp, INT_CAUSE_EXT(port_num));
+ wrl(mp, INT_CAUSE(mp->port_num), 0);
+ wrl(mp, INT_CAUSE_EXT(mp->port_num), 0);
+ rdl(mp, INT_CAUSE_EXT(mp->port_num));
- err = request_irq(dev->irq, mv643xx_eth_int_handler,
- IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
+ err = request_irq(dev->irq, mv643xx_eth_irq,
+ IRQF_SHARED | IRQF_SAMPLE_RANDOM,
+ dev->name, dev);
if (err) {
- printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
+ dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
return -EAGAIN;
}
- port_init(mp);
+ init_mac_tables(mp);
- err = rxq_init(mp);
- if (err)
- goto out_free_irq;
- rxq_refill(mp->rxq);
+ for (i = 0; i < 8; i++) {
+ if ((mp->rxq_mask & (1 << i)) == 0)
+ continue;
- mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
- GFP_KERNEL);
- if (!mp->tx_skb) {
- printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
- err = -ENOMEM;
- goto out_free_rx_skb;
+ err = rxq_init(mp, i);
+ if (err) {
+ while (--i >= 0)
+ if (mp->rxq_mask & (1 << i))
+ rxq_deinit(mp->rxq + i);
+ goto out;
+ }
+
+ rxq_refill(mp->rxq + i);
}
- /* Allocate TX ring */
- mp->tx_desc_count = 0;
- size = mp->tx_ring_size * sizeof(struct tx_desc);
- mp->tx_desc_area_size = size;
-
- if (mp->tx_sram_size) {
- mp->tx_desc_area = ioremap(mp->tx_sram_addr,
- mp->tx_sram_size);
- mp->tx_desc_dma = mp->tx_sram_addr;
- } else
- mp->tx_desc_area = dma_alloc_coherent(NULL, size,
- &mp->tx_desc_dma,
- GFP_KERNEL);
+ for (i = 0; i < 8; i++) {
+ if ((mp->txq_mask & (1 << i)) == 0)
+ continue;
- if (!mp->tx_desc_area) {
- printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
- dev->name, size);
- err = -ENOMEM;
- goto out_free_tx_skb;
+ err = txq_init(mp, i);
+ if (err) {
+ while (--i >= 0)
+ if (mp->txq_mask & (1 << i))
+ txq_deinit(mp->txq + i);
+ goto out_free;
+ }
}
- BUG_ON((u32) mp->tx_desc_area & 0xf); /* check 16-byte alignment */
- memset((void *)mp->tx_desc_area, 0, mp->tx_desc_area_size);
-
- ether_init_tx_desc_ring(mp);
#ifdef MV643XX_ETH_NAPI
napi_enable(&mp->napi);
#endif
- port_start(dev);
-
- /* Interrupt Coalescing */
-
-#ifdef MV643XX_ETH_COAL
- mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
-#endif
+ port_start(mp);
- mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
+ set_rx_coal(mp, 0);
+ set_tx_coal(mp, 0);
- /* Unmask phy and link status changes interrupts */
- wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
+ wrl(mp, INT_MASK_EXT(mp->port_num),
+ INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
- /* Unmask RX buffer and TX end interrupt */
- wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
+ wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_EXT);
return 0;
-out_free_tx_skb:
- kfree(mp->tx_skb);
-out_free_rx_skb:
- rxq_deinit(mp->rxq);
-out_free_irq:
+
+out_free:
+ for (i = 0; i < 8; i++)
+ if (mp->rxq_mask & (1 << i))
+ rxq_deinit(mp->rxq + i);
+out:
free_irq(dev->irq, dev);
return err;
static void port_reset(struct mv643xx_eth_private *mp)
{
- unsigned int port_num = mp->port_num;
- unsigned int reg_data;
-
- mv643xx_eth_port_disable_tx(mp);
- rxq_disable(mp->rxq);
+ unsigned int data;
+ int i;
- /* Clear all MIB counters */
- clear_mib_counters(mp);
+ for (i = 0; i < 8; i++) {
+ if (mp->rxq_mask & (1 << i))
+ rxq_disable(mp->rxq + i);
+ if (mp->txq_mask & (1 << i))
+ txq_disable(mp->txq + i);
+ }
+ while (!(rdl(mp, PORT_STATUS(mp->port_num)) & TX_FIFO_EMPTY))
+ udelay(10);
/* Reset the Enable bit in the Configuration Register */
- reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
- reg_data &= ~(SERIAL_PORT_ENABLE |
- DO_NOT_FORCE_LINK_FAIL |
- FORCE_LINK_PASS);
- wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
+ data = rdl(mp, PORT_SERIAL_CONTROL(mp->port_num));
+ data &= ~(SERIAL_PORT_ENABLE |
+ DO_NOT_FORCE_LINK_FAIL |
+ FORCE_LINK_PASS);
+ wrl(mp, PORT_SERIAL_CONTROL(mp->port_num), data);
}
static int mv643xx_eth_stop(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
+ int i;
- /* Mask all interrupts on ethernet port */
- wrl(mp, INT_MASK(port_num), 0x00000000);
- /* wait for previous write to complete */
- rdl(mp, INT_MASK(port_num));
+ wrl(mp, INT_MASK(mp->port_num), 0x00000000);
+ rdl(mp, INT_MASK(mp->port_num));
#ifdef MV643XX_ETH_NAPI
napi_disable(&mp->napi);
netif_carrier_off(dev);
netif_stop_queue(dev);
- port_reset(mp);
+ free_irq(dev->irq, dev);
- mv643xx_eth_free_tx_rings(dev);
- rxq_deinit(mp->rxq);
+ port_reset(mp);
+ mib_counters_update(mp);
- free_irq(dev->irq, dev);
+ for (i = 0; i < 8; i++) {
+ if (mp->rxq_mask & (1 << i))
+ rxq_deinit(mp->rxq + i);
+ if (mp->txq_mask & (1 << i))
+ txq_deinit(mp->txq + i);
+ }
return 0;
}
-static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
+static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
+ if (mp->phy_addr != -1)
+ return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
+
+ return -EOPNOTSUPP;
}
static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
{
- if ((new_mtu > 9500) || (new_mtu < 64))
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
+
+ if (new_mtu < 64 || new_mtu > 9500)
return -EINVAL;
dev->mtu = new_mtu;
+ tx_set_rate(mp, 1000000000, 16777216);
+
if (!netif_running(dev))
return 0;
* Stop and then re-open the interface. This will allocate RX
* skbs of the new MTU.
* There is a possible danger that the open will not succeed,
- * due to memory being full, which might fail the open function.
+ * due to memory being full.
*/
mv643xx_eth_stop(dev);
if (mv643xx_eth_open(dev)) {
- printk(KERN_ERR "%s: Fatal error on opening device\n",
- dev->name);
+ dev_printk(KERN_ERR, &dev->dev,
+ "fatal error on re-opening device after "
+ "MTU change\n");
}
return 0;
}
-static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
+static void tx_timeout_task(struct work_struct *ugly)
{
- struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
- tx_timeout_task);
- struct net_device *dev = mp->dev;
-
- if (!netif_running(dev))
- return;
+ struct mv643xx_eth_private *mp;
- netif_stop_queue(dev);
+ mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
+ if (netif_running(mp->dev)) {
+ netif_stop_queue(mp->dev);
- port_reset(mp);
- port_start(dev);
+ port_reset(mp);
+ port_start(mp);
- if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
- netif_wake_queue(dev);
+ __txq_maybe_wake(mp->txq + mp->txq_primary);
+ }
}
static void mv643xx_eth_tx_timeout(struct net_device *dev)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- printk(KERN_INFO "%s: TX timeout ", dev->name);
+ dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
- /* Do the reset outside of interrupt context */
schedule_work(&mp->tx_timeout_task);
}
#ifdef CONFIG_NET_POLL_CONTROLLER
-static void mv643xx_eth_netpoll(struct net_device *netdev)
+static void mv643xx_eth_netpoll(struct net_device *dev)
{
- struct mv643xx_eth_private *mp = netdev_priv(netdev);
- int port_num = mp->port_num;
+ struct mv643xx_eth_private *mp = netdev_priv(dev);
- wrl(mp, INT_MASK(port_num), 0x00000000);
- /* wait for previous write to complete */
- rdl(mp, INT_MASK(port_num));
+ wrl(mp, INT_MASK(mp->port_num), 0x00000000);
+ rdl(mp, INT_MASK(mp->port_num));
- mv643xx_eth_int_handler(netdev->irq, netdev);
+ mv643xx_eth_irq(dev->irq, dev);
- wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
+ wrl(mp, INT_MASK(mp->port_num), INT_TX_END | INT_RX | INT_CAUSE_EXT);
}
#endif
-static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
+static int mv643xx_eth_mdio_read(struct net_device *dev, int addr, int reg)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
int val;
- read_smi_reg(mp, location, &val);
+ smi_reg_read(mp, addr, reg, &val);
+
return val;
}
-static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
+static void mv643xx_eth_mdio_write(struct net_device *dev, int addr, int reg, int val)
{
struct mv643xx_eth_private *mp = netdev_priv(dev);
- write_smi_reg(mp, location, val);
+ smi_reg_write(mp, addr, reg, val);
}
msp->win_protect = win_protect;
}
+static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
+{
+ /*
+ * Check whether we have a 14-bit coal limit field in bits
+ * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
+ * SDMA config register.
+ */
+ writel(0x02000000, msp->base + SDMA_CONFIG(0));
+ if (readl(msp->base + SDMA_CONFIG(0)) & 0x02000000)
+ msp->extended_rx_coal_limit = 1;
+ else
+ msp->extended_rx_coal_limit = 0;
+
+ /*
+ * Check whether the TX rate control registers are in the
+ * old or the new place.
+ */
+ writel(1, msp->base + TX_BW_MTU_MOVED(0));
+ if (readl(msp->base + TX_BW_MTU_MOVED(0)) & 1)
+ msp->tx_bw_control_moved = 1;
+ else
+ msp->tx_bw_control_moved = 0;
+}
+
static int mv643xx_eth_shared_probe(struct platform_device *pdev)
{
static int mv643xx_eth_version_printed = 0;
goto out_free;
spin_lock_init(&msp->phy_lock);
- msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
-
- platform_set_drvdata(pdev, msp);
/*
* (Re-)program MBUS remapping windows if we are asked to.
if (pd != NULL && pd->dram != NULL)
mv643xx_eth_conf_mbus_windows(msp, pd->dram);
+ /*
+ * Detect hardware parameters.
+ */
+ msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
+ infer_hw_params(msp);
+
+ platform_set_drvdata(pdev, msp);
+
return 0;
out_free:
}
static struct platform_driver mv643xx_eth_shared_driver = {
- .probe = mv643xx_eth_shared_probe,
- .remove = mv643xx_eth_shared_remove,
+ .probe = mv643xx_eth_shared_probe,
+ .remove = mv643xx_eth_shared_remove,
.driver = {
- .name = MV643XX_ETH_SHARED_NAME,
+ .name = MV643XX_ETH_SHARED_NAME,
.owner = THIS_MODULE,
},
};
static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
{
- u32 reg_data;
int addr_shift = 5 * mp->port_num;
+ u32 data;
- reg_data = rdl(mp, PHY_ADDR);
- reg_data &= ~(0x1f << addr_shift);
- reg_data |= (phy_addr & 0x1f) << addr_shift;
- wrl(mp, PHY_ADDR, reg_data);
+ data = rdl(mp, PHY_ADDR);
+ data &= ~(0x1f << addr_shift);
+ data |= (phy_addr & 0x1f) << addr_shift;
+ wrl(mp, PHY_ADDR, data);
}
static int phy_addr_get(struct mv643xx_eth_private *mp)
{
- unsigned int reg_data;
+ unsigned int data;
+
+ data = rdl(mp, PHY_ADDR);
+
+ return (data >> (5 * mp->port_num)) & 0x1f;
+}
+
+static void set_params(struct mv643xx_eth_private *mp,
+ struct mv643xx_eth_platform_data *pd)
+{
+ struct net_device *dev = mp->dev;
+
+ if (is_valid_ether_addr(pd->mac_addr))
+ memcpy(dev->dev_addr, pd->mac_addr, 6);
+ else
+ uc_addr_get(mp, dev->dev_addr);
+
+ if (pd->phy_addr == -1) {
+ mp->shared_smi = NULL;
+ mp->phy_addr = -1;
+ } else {
+ mp->shared_smi = mp->shared;
+ if (pd->shared_smi != NULL)
+ mp->shared_smi = platform_get_drvdata(pd->shared_smi);
+
+ if (pd->force_phy_addr || pd->phy_addr) {
+ mp->phy_addr = pd->phy_addr & 0x3f;
+ phy_addr_set(mp, mp->phy_addr);
+ } else {
+ mp->phy_addr = phy_addr_get(mp);
+ }
+ }
+
+ mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
+ if (pd->rx_queue_size)
+ mp->default_rx_ring_size = pd->rx_queue_size;
+ mp->rx_desc_sram_addr = pd->rx_sram_addr;
+ mp->rx_desc_sram_size = pd->rx_sram_size;
+
+ if (pd->rx_queue_mask)
+ mp->rxq_mask = pd->rx_queue_mask;
+ else
+ mp->rxq_mask = 0x01;
+ mp->rxq_primary = fls(mp->rxq_mask) - 1;
- reg_data = rdl(mp, PHY_ADDR);
+ mp->default_tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
+ if (pd->tx_queue_size)
+ mp->default_tx_ring_size = pd->tx_queue_size;
+ mp->tx_desc_sram_addr = pd->tx_sram_addr;
+ mp->tx_desc_sram_size = pd->tx_sram_size;
- return ((reg_data >> (5 * mp->port_num)) & 0x1f);
+ if (pd->tx_queue_mask)
+ mp->txq_mask = pd->tx_queue_mask;
+ else
+ mp->txq_mask = 0x01;
+ mp->txq_primary = fls(mp->txq_mask) - 1;
}
static int phy_detect(struct mv643xx_eth_private *mp)
{
- unsigned int phy_reg_data0;
- int auto_neg;
+ unsigned int data;
+ unsigned int data2;
+
+ smi_reg_read(mp, mp->phy_addr, 0, &data);
+ smi_reg_write(mp, mp->phy_addr, 0, data ^ 0x1000);
- read_smi_reg(mp, 0, &phy_reg_data0);
- auto_neg = phy_reg_data0 & 0x1000;
- phy_reg_data0 ^= 0x1000; /* invert auto_neg */
- write_smi_reg(mp, 0, phy_reg_data0);
+ smi_reg_read(mp, mp->phy_addr, 0, &data2);
+ if (((data ^ data2) & 0x1000) == 0)
+ return -ENODEV;
- read_smi_reg(mp, 0, &phy_reg_data0);
- if ((phy_reg_data0 & 0x1000) == auto_neg)
- return -ENODEV; /* change didn't take */
+ smi_reg_write(mp, mp->phy_addr, 0, data);
- phy_reg_data0 ^= 0x1000;
- write_smi_reg(mp, 0, phy_reg_data0);
return 0;
}
-static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
- int speed, int duplex,
- struct ethtool_cmd *cmd)
+static int phy_init(struct mv643xx_eth_private *mp,
+ struct mv643xx_eth_platform_data *pd)
{
- struct mv643xx_eth_private *mp = netdev_priv(dev);
+ struct ethtool_cmd cmd;
+ int err;
- memset(cmd, 0, sizeof(*cmd));
+ err = phy_detect(mp);
+ if (err) {
+ dev_printk(KERN_INFO, &mp->dev->dev,
+ "no PHY detected at addr %d\n", mp->phy_addr);
+ return err;
+ }
+ phy_reset(mp);
- cmd->port = PORT_MII;
- cmd->transceiver = XCVR_INTERNAL;
- cmd->phy_address = phy_address;
-
- if (speed == 0) {
- cmd->autoneg = AUTONEG_ENABLE;
- /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
- cmd->speed = SPEED_100;
- cmd->advertising = ADVERTISED_10baseT_Half |
- ADVERTISED_10baseT_Full |
- ADVERTISED_100baseT_Half |
- ADVERTISED_100baseT_Full;
+ mp->mii.phy_id = mp->phy_addr;
+ mp->mii.phy_id_mask = 0x3f;
+ mp->mii.reg_num_mask = 0x1f;
+ mp->mii.dev = mp->dev;
+ mp->mii.mdio_read = mv643xx_eth_mdio_read;
+ mp->mii.mdio_write = mv643xx_eth_mdio_write;
+
+ mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
+
+ memset(&cmd, 0, sizeof(cmd));
+
+ cmd.port = PORT_MII;
+ cmd.transceiver = XCVR_INTERNAL;
+ cmd.phy_address = mp->phy_addr;
+ if (pd->speed == 0) {
+ cmd.autoneg = AUTONEG_ENABLE;
+ cmd.speed = SPEED_100;
+ cmd.advertising = ADVERTISED_10baseT_Half |
+ ADVERTISED_10baseT_Full |
+ ADVERTISED_100baseT_Half |
+ ADVERTISED_100baseT_Full;
if (mp->mii.supports_gmii)
- cmd->advertising |= ADVERTISED_1000baseT_Full;
+ cmd.advertising |= ADVERTISED_1000baseT_Full;
} else {
- cmd->autoneg = AUTONEG_DISABLE;
- cmd->speed = speed;
- cmd->duplex = duplex;
+ cmd.autoneg = AUTONEG_DISABLE;
+ cmd.speed = pd->speed;
+ cmd.duplex = pd->duplex;
}
+
+ update_pscr(mp, cmd.speed, cmd.duplex);
+ mv643xx_eth_set_settings(mp->dev, &cmd);
+
+ return 0;
}
static int mv643xx_eth_probe(struct platform_device *pdev)
{
struct mv643xx_eth_platform_data *pd;
- int port_num;
struct mv643xx_eth_private *mp;
struct net_device *dev;
- u8 *p;
struct resource *res;
- int err;
- struct ethtool_cmd cmd;
- int duplex = DUPLEX_HALF;
- int speed = 0; /* default to auto-negotiation */
DECLARE_MAC_BUF(mac);
+ int err;
pd = pdev->dev.platform_data;
if (pd == NULL) {
- printk(KERN_ERR "No mv643xx_eth_platform_data\n");
+ dev_printk(KERN_ERR, &pdev->dev,
+ "no mv643xx_eth_platform_data\n");
return -ENODEV;
}
if (pd->shared == NULL) {
- printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
+ dev_printk(KERN_ERR, &pdev->dev,
+ "no mv643xx_eth_platform_data->shared\n");
return -ENODEV;
}
if (!dev)
return -ENOMEM;
- platform_set_drvdata(pdev, dev);
-
mp = netdev_priv(dev);
+ platform_set_drvdata(pdev, mp);
+
+ mp->shared = platform_get_drvdata(pd->shared);
+ mp->port_num = pd->port_number;
+
mp->dev = dev;
#ifdef MV643XX_ETH_NAPI
netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
#endif
+ set_params(mp, pd);
+
+ spin_lock_init(&mp->lock);
+
+ mib_counters_clear(mp);
+ INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
+
+ if (mp->phy_addr != -1) {
+ err = phy_init(mp, pd);
+ if (err)
+ goto out;
+
+ SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
+ } else {
+ SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops_phyless);
+ }
+
+
res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
BUG_ON(!res);
dev->irq = res->start;
+ dev->hard_start_xmit = mv643xx_eth_xmit;
dev->open = mv643xx_eth_open;
dev->stop = mv643xx_eth_stop;
- dev->hard_start_xmit = mv643xx_eth_start_xmit;
- dev->set_mac_address = mv643xx_eth_set_mac_address;
dev->set_multicast_list = mv643xx_eth_set_rx_mode;
-
- /* No need to Tx Timeout */
+ dev->set_mac_address = mv643xx_eth_set_mac_address;
+ dev->do_ioctl = mv643xx_eth_ioctl;
+ dev->change_mtu = mv643xx_eth_change_mtu;
dev->tx_timeout = mv643xx_eth_tx_timeout;
-
#ifdef CONFIG_NET_POLL_CONTROLLER
dev->poll_controller = mv643xx_eth_netpoll;
#endif
-
dev->watchdog_timeo = 2 * HZ;
dev->base_addr = 0;
- dev->change_mtu = mv643xx_eth_change_mtu;
- dev->do_ioctl = mv643xx_eth_do_ioctl;
- SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
-#ifdef MAX_SKB_FRAGS
/*
* Zero copy can only work if we use Discovery II memory. Else, we will
* have to map the buffers to ISA memory which is only 16 MB
*/
dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
#endif
-#endif
-
- /* Configure the timeout task */
- INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
-
- spin_lock_init(&mp->lock);
- mp->shared = platform_get_drvdata(pd->shared);
- port_num = mp->port_num = pd->port_number;
+ SET_NETDEV_DEV(dev, &pdev->dev);
if (mp->shared->win_protect)
- wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
-
- mp->shared_smi = mp->shared;
- if (pd->shared_smi != NULL)
- mp->shared_smi = platform_get_drvdata(pd->shared_smi);
-
- /* set default config values */
- uc_addr_get(mp, dev->dev_addr);
- mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
-
- if (is_valid_ether_addr(pd->mac_addr))
- memcpy(dev->dev_addr, pd->mac_addr, 6);
-
- if (pd->phy_addr || pd->force_phy_addr)
- phy_addr_set(mp, pd->phy_addr);
-
- mp->default_rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
- if (pd->rx_queue_size)
- mp->default_rx_ring_size = pd->rx_queue_size;
-
- if (pd->tx_queue_size)
- mp->tx_ring_size = pd->tx_queue_size;
-
- if (pd->tx_sram_size) {
- mp->tx_sram_size = pd->tx_sram_size;
- mp->tx_sram_addr = pd->tx_sram_addr;
- }
-
- if (pd->rx_sram_size) {
- mp->rx_desc_sram_addr = pd->rx_sram_addr;
- mp->rx_desc_sram_size = pd->rx_sram_size;
- }
-
- duplex = pd->duplex;
- speed = pd->speed;
+ wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
- /* Hook up MII support for ethtool */
- mp->mii.dev = dev;
- mp->mii.mdio_read = mv643xx_eth_mdio_read;
- mp->mii.mdio_write = mv643xx_eth_mdio_write;
- mp->mii.phy_id = phy_addr_get(mp);
- mp->mii.phy_id_mask = 0x3f;
- mp->mii.reg_num_mask = 0x1f;
-
- err = phy_detect(mp);
- if (err) {
- pr_debug("%s: No PHY detected at addr %d\n",
- dev->name, phy_addr_get(mp));
- goto out;
- }
-
- phy_reset(mp);
- mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
- mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
- mv643xx_eth_update_pscr(dev, &cmd);
- mv643xx_eth_set_settings(dev, &cmd);
-
- SET_NETDEV_DEV(dev, &pdev->dev);
err = register_netdev(dev);
if (err)
goto out;
- p = dev->dev_addr;
- printk(KERN_NOTICE
- "%s: port %d with MAC address %s\n",
- dev->name, port_num, print_mac(mac, p));
+ dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %s\n",
+ mp->port_num, print_mac(mac, dev->dev_addr));
if (dev->features & NETIF_F_SG)
- printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
+ dev_printk(KERN_NOTICE, &dev->dev, "scatter/gather enabled\n");
if (dev->features & NETIF_F_IP_CSUM)
- printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
- dev->name);
-
-#ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
- printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
-#endif
-
-#ifdef MV643XX_ETH_COAL
- printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
- dev->name);
-#endif
+ dev_printk(KERN_NOTICE, &dev->dev, "tx checksum offload\n");
#ifdef MV643XX_ETH_NAPI
- printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
+ dev_printk(KERN_NOTICE, &dev->dev, "napi enabled\n");
#endif
- if (mp->tx_sram_size > 0)
- printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
+ if (mp->tx_desc_sram_size > 0)
+ dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
return 0;
static int mv643xx_eth_remove(struct platform_device *pdev)
{
- struct net_device *dev = platform_get_drvdata(pdev);
+ struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
- unregister_netdev(dev);
+ unregister_netdev(mp->dev);
flush_scheduled_work();
+ free_netdev(mp->dev);
- free_netdev(dev);
platform_set_drvdata(pdev, NULL);
+
return 0;
}
static void mv643xx_eth_shutdown(struct platform_device *pdev)
{
- struct net_device *dev = platform_get_drvdata(pdev);
- struct mv643xx_eth_private *mp = netdev_priv(dev);
- unsigned int port_num = mp->port_num;
+ struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
/* Mask all interrupts on ethernet port */
- wrl(mp, INT_MASK(port_num), 0);
- rdl(mp, INT_MASK(port_num));
+ wrl(mp, INT_MASK(mp->port_num), 0);
+ rdl(mp, INT_MASK(mp->port_num));
- port_reset(mp);
+ if (netif_running(mp->dev))
+ port_reset(mp);
}
static struct platform_driver mv643xx_eth_driver = {
- .probe = mv643xx_eth_probe,
- .remove = mv643xx_eth_remove,
- .shutdown = mv643xx_eth_shutdown,
+ .probe = mv643xx_eth_probe,
+ .remove = mv643xx_eth_remove,
+ .shutdown = mv643xx_eth_shutdown,
.driver = {
- .name = MV643XX_ETH_NAME,
+ .name = MV643XX_ETH_NAME,
.owner = THIS_MODULE,
},
};
if (rc)
platform_driver_unregister(&mv643xx_eth_shared_driver);
}
+
return rc;
}
+module_init(mv643xx_eth_init_module);
static void __exit mv643xx_eth_cleanup_module(void)
{
platform_driver_unregister(&mv643xx_eth_driver);
platform_driver_unregister(&mv643xx_eth_shared_driver);
}
-
-module_init(mv643xx_eth_init_module);
module_exit(mv643xx_eth_cleanup_module);
-MODULE_LICENSE("GPL");
-MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
- " and Dale Farnsworth");
+MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
+ "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
-MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
+MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
+MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
projects / linux-2.6 / blobdiff