u32 stat_GenStat13;
u32 stat_GenStat14;
u32 stat_GenStat15;
+ u32 stat_FwRxDrop;
};
#define BNX2_COM_SCRATCH 0x00120000
+#define BNX2_FW_RX_DROP_COUNT 0x00120084
+
/*
* cp_reg definition
#define DMA_READ_CHANS 5
#define DMA_WRITE_CHANS 3
-#define BCM_PAGE_BITS 12
+/* Use CPU native page size up to 16K for the ring sizes. */
+#if (PAGE_SHIFT > 14)
+#define BCM_PAGE_BITS 14
+#else
+#define BCM_PAGE_BITS PAGE_SHIFT
+#endif
#define BCM_PAGE_SIZE (1 << BCM_PAGE_BITS)
#define TX_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct tx_bd))
#define RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
-#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> 8)
+#define RX_RING(x) (((x) & ~MAX_RX_DESC_CNT) >> (BCM_PAGE_BITS - 4))
#define RX_IDX(x) ((x) & MAX_RX_DESC_CNT)
/* Context size. */
#define USING_MSI_FLAG 0x20
#define ASF_ENABLE_FLAG 0x40
- struct tx_bd *tx_desc_ring;
- struct sw_bd *tx_buf_ring;
- u32 tx_prod_bseq;
- u16 tx_prod;
- u16 tx_cons;
- int tx_ring_size;
+ /* Put tx producer and consumer fields in separate cache lines. */
- u16 hw_tx_cons;
- u16 hw_rx_cons;
+ u32 tx_prod_bseq __attribute__((aligned(L1_CACHE_BYTES)));
+ u16 tx_prod;
+
+ u16 tx_cons __attribute__((aligned(L1_CACHE_BYTES)));
+ u16 hw_tx_cons;
#ifdef BCM_VLAN
struct vlan_group *vlgrp;
u32 rx_prod_bseq;
u16 rx_prod;
u16 rx_cons;
+ u16 hw_rx_cons;
u32 rx_csum;
struct sw_bd *rx_buf_ring;
struct rx_bd *rx_desc_ring[MAX_RX_RINGS];
- /* Only used to synchronize netif_stop_queue/wake_queue when tx */
- /* ring is full */
- spinlock_t tx_lock;
+ /* TX constants */
+ struct tx_bd *tx_desc_ring;
+ struct sw_bd *tx_buf_ring;
+ int tx_ring_size;
+ u32 tx_wake_thresh;
/* End of fields used in the performance code paths. */
u32 flash_size;
int status_stats_size;
+
+ struct z_stream_s *strm;
+ void *gunzip_buf;
};
static u32 bnx2_reg_rd_ind(struct bnx2 *bp, u32 offset);
#define BNX2_DRV_MSG_CODE_PULSE 0x06000000
#define BNX2_DRV_MSG_CODE_DIAG 0x07000000
#define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
+#define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
#define BNX2_DRV_MSG_DATA 0x00ff0000
#define BNX2_DRV_MSG_DATA_WAIT0 0x00010000