[PATCH] bnx2: refine bnx2_poll

[linux-2.6] / drivers / net / bnx2.h

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index c0e88f850493b9ccb897aa639b89c66e8674a6ec..76bb5f1a250bd52f43567e54bcf6f71efc720344 100644 (file)
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -3715,6 +3715,15 @@ struct l2_fhdr {
 #define BNX2_MCP_ROM                                   0x00150000
 #define BNX2_MCP_SCRATCH                               0x00160000
 
+#define BNX2_SHM_HDR_SIGNATURE                         BNX2_MCP_SCRATCH
+#define BNX2_SHM_HDR_SIGNATURE_SIG_MASK                         0xffff0000
+#define BNX2_SHM_HDR_SIGNATURE_SIG                      0x53530000
+#define BNX2_SHM_HDR_SIGNATURE_VER_MASK                         0x000000ff
+#define BNX2_SHM_HDR_SIGNATURE_VER_ONE                  0x00000001
+
+#define BNX2_SHM_HDR_ADDR_0                            BNX2_MCP_SCRATCH + 4
+#define BNX2_SHM_HDR_ADDR_1                            BNX2_MCP_SCRATCH + 8
+
 
 #define NUM_MC_HASH_REGISTERS   8
 
@@ -3847,7 +3856,7 @@ struct sw_bd {
 #define BUFFERED_FLASH_PHY_PAGE_SIZE           (1 << BUFFERED_FLASH_PAGE_BITS)
 #define BUFFERED_FLASH_BYTE_ADDR_MASK          (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
 #define BUFFERED_FLASH_PAGE_SIZE               264
-#define BUFFERED_FLASH_TOTAL_SIZE              131072
+#define BUFFERED_FLASH_TOTAL_SIZE              0x21000
 
 #define SAIFUN_FLASH_PAGE_BITS                 8
 #define SAIFUN_FLASH_PHY_PAGE_SIZE             (1 << SAIFUN_FLASH_PAGE_BITS)
@@ -3855,6 +3864,12 @@ struct sw_bd {
 #define SAIFUN_FLASH_PAGE_SIZE                 256
 #define SAIFUN_FLASH_BASE_TOTAL_SIZE           65536
 
+#define ST_MICRO_FLASH_PAGE_BITS               8
+#define ST_MICRO_FLASH_PHY_PAGE_SIZE           (1 << ST_MICRO_FLASH_PAGE_BITS)
+#define ST_MICRO_FLASH_BYTE_ADDR_MASK          (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
+#define ST_MICRO_FLASH_PAGE_SIZE               256
+#define ST_MICRO_FLASH_BASE_TOTAL_SIZE         65536
+
 #define NVRAM_TIMEOUT_COUNT                    30000
 
 
@@ -3863,6 +3878,8 @@ struct sw_bd {
                                                 BNX2_NVM_CFG1_PROTECT_MODE | \
                                                 BNX2_NVM_CFG1_FLASH_SIZE)
 
+#define FLASH_BACKUP_STRAP_MASK                        (0xf << 26)
+
 struct flash_spec {
        u32 strapping;
        u32 config1;
@@ -3897,6 +3914,9 @@ struct bnx2 {
        u16                     tx_cons;
        int                     tx_ring_size;
 
+       u16                     hw_tx_cons;
+       u16                     hw_rx_cons;
+
 #ifdef BCM_VLAN 
        struct                  vlan_group *vlgrp;
 #endif
@@ -4044,6 +4064,8 @@ struct bnx2 {
 
        u8                      mac_addr[8];
 
+       u32                     shmem_base;
+
        u32                     fw_ver;
 
        int                     pm_cap;
@@ -4183,6 +4205,38 @@ struct fw_info {
 #define BNX2_FW_MSG_STATUS_FAILURE              0x00ff0000
 
 #define BNX2_LINK_STATUS                       0x0000000c
+#define BNX2_LINK_STATUS_INIT_VALUE             0xffffffff 
+#define BNX2_LINK_STATUS_LINK_UP                0x1 
+#define BNX2_LINK_STATUS_LINK_DOWN              0x0 
+#define BNX2_LINK_STATUS_SPEED_MASK             0x1e
+#define BNX2_LINK_STATUS_AN_INCOMPLETE          (0<<1) 
+#define BNX2_LINK_STATUS_10HALF                         (1<<1) 
+#define BNX2_LINK_STATUS_10FULL                         (2<<1) 
+#define BNX2_LINK_STATUS_100HALF                (3<<1) 
+#define BNX2_LINK_STATUS_100BASE_T4             (4<<1) 
+#define BNX2_LINK_STATUS_100FULL                (5<<1) 
+#define BNX2_LINK_STATUS_1000HALF               (6<<1) 
+#define BNX2_LINK_STATUS_1000FULL               (7<<1) 
+#define BNX2_LINK_STATUS_2500HALF               (8<<1) 
+#define BNX2_LINK_STATUS_2500FULL               (9<<1) 
+#define BNX2_LINK_STATUS_AN_ENABLED             (1<<5) 
+#define BNX2_LINK_STATUS_AN_COMPLETE            (1<<6) 
+#define BNX2_LINK_STATUS_PARALLEL_DET           (1<<7) 
+#define BNX2_LINK_STATUS_RESERVED               (1<<8) 
+#define BNX2_LINK_STATUS_PARTNER_AD_1000FULL    (1<<9) 
+#define BNX2_LINK_STATUS_PARTNER_AD_1000HALF    (1<<10) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100BT4      (1<<11) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100FULL     (1<<12) 
+#define BNX2_LINK_STATUS_PARTNER_AD_100HALF     (1<<13) 
+#define BNX2_LINK_STATUS_PARTNER_AD_10FULL      (1<<14) 
+#define BNX2_LINK_STATUS_PARTNER_AD_10HALF      (1<<15) 
+#define BNX2_LINK_STATUS_TX_FC_ENABLED          (1<<16) 
+#define BNX2_LINK_STATUS_RX_FC_ENABLED          (1<<17) 
+#define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP  (1<<18) 
+#define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP         (1<<19) 
+#define BNX2_LINK_STATUS_SERDES_LINK            (1<<20) 
+#define BNX2_LINK_STATUS_PARTNER_AD_2500FULL    (1<<21) 
+#define BNX2_LINK_STATUS_PARTNER_AD_2500HALF    (1<<22) 
 
 #define BNX2_DRV_PULSE_MB                      0x00000010
 #define BNX2_DRV_PULSE_SEQ_MASK                         0x00007fff