[Blackfin] arch: Add proper SW System Reset delay sequence

[linux-2.6] / drivers / net / bnx2.h

diff --git a/drivers/net/bnx2.h b/drivers/net/bnx2.h
index a717459cc8d46b966153750e90f452520147cae3..30ba366608b0dd4f1e83ca59ee881f0979e562c0 100644 (file)
--- a/drivers/net/bnx2.h
+++ b/drivers/net/bnx2.h
@@ -6513,7 +6513,6 @@ struct bnx2 {
        u32                     rx_prod_bseq;
        u16                     rx_prod;
        u16                     rx_cons;
-       u16                     hw_rx_cons;
 
        u32                     rx_csum;
 
@@ -6738,7 +6737,7 @@ struct fw_info {
        const u32 text_addr;
        const u32 text_len;
        const u32 text_index;
-/*     u32 *text;*/
+       u32 *text;
        u8 *gz_text;
        const u32 gz_text_len;
 
@@ -6752,13 +6751,11 @@ struct fw_info {
        const u32 sbss_addr;
        const u32 sbss_len;
        const u32 sbss_index;
-       const u32 *sbss;
 
        /* BSS section. */
        const u32 bss_addr;
        const u32 bss_len;
        const u32 bss_index;
-       const u32 *bss;
 
        /* Read-only section. */
        const u32 rodata_addr;
@@ -6910,6 +6907,7 @@ struct fw_info {
 #define BNX2_SHARED_HW_CFG_LED_MODE_MAC                 0
 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1       0x100
 #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2       0x200
+#define BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX     0x8000
 
 #define BNX2_SHARED_HW_CFG_CONFIG2             0x00000040
 #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK       0x00fff000