[BNX2]: Fix UDP checksum verification

[linux-2.6] / drivers / net / bnx2.c

diff --git a/drivers/net/bnx2.c b/drivers/net/bnx2.c
index 790dc926acae68872252530262bc0b9d68efc20f..ec08f833c32d44c240294b48eba27dba12929ccf 100644 (file)
--- a/drivers/net/bnx2.c
+++ b/drivers/net/bnx2.c
@@ -1171,7 +1171,8 @@ bnx2_init_5708s_phy(struct bnx2 *bp)
        }
 
        if ((CHIP_ID(bp) == CHIP_ID_5708_A0) ||
-           (CHIP_ID(bp) == CHIP_ID_5708_B0)) {
+           (CHIP_ID(bp) == CHIP_ID_5708_B0) ||
+           (CHIP_ID(bp) == CHIP_ID_5708_B1)) {
                /* increase tx signal amplitude */
                bnx2_write_phy(bp, BCM5708S_BLK_ADDR,
                               BCM5708S_BLK_ADDR_TX_MISC);
@@ -1327,43 +1328,45 @@ bnx2_set_mac_loopback(struct bnx2 *bp)
 }
 
 static int
-bnx2_fw_sync(struct bnx2 *bp, u32 msg_data)
+bnx2_fw_sync(struct bnx2 *bp, u32 msg_data, int silent)
 {
        int i;
        u32 val;
 
-       if (bp->fw_timed_out)
-               return -EBUSY;
-
        bp->fw_wr_seq++;
        msg_data |= bp->fw_wr_seq;
 
        REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
 
        /* wait for an acknowledgement. */
-       for (i = 0; i < (FW_ACK_TIME_OUT_MS * 1000)/5; i++) {
-               udelay(5);
+       for (i = 0; i < (FW_ACK_TIME_OUT_MS / 10); i++) {
+               msleep(10);
 
                val = REG_RD_IND(bp, bp->shmem_base + BNX2_FW_MB);
 
                if ((val & BNX2_FW_MSG_ACK) == (msg_data & BNX2_DRV_MSG_SEQ))
                        break;
        }
+       if ((msg_data & BNX2_DRV_MSG_DATA) == BNX2_DRV_MSG_DATA_WAIT0)
+               return 0;
 
        /* If we timed out, inform the firmware that this is the case. */
-       if (((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) &&
-               ((msg_data & BNX2_DRV_MSG_DATA) != BNX2_DRV_MSG_DATA_WAIT0)) {
+       if ((val & BNX2_FW_MSG_ACK) != (msg_data & BNX2_DRV_MSG_SEQ)) {
+               if (!silent)
+                       printk(KERN_ERR PFX "fw sync timeout, reset code = "
+                                           "%x\n", msg_data);
 
                msg_data &= ~BNX2_DRV_MSG_CODE;
                msg_data |= BNX2_DRV_MSG_CODE_FW_TIMEOUT;
 
                REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_MB, msg_data);
 
-               bp->fw_timed_out = 1;
-
                return -EBUSY;
        }
 
+       if ((val & BNX2_FW_MSG_STATUS_MASK) != BNX2_FW_MSG_STATUS_OK)
+               return -EIO;
+
        return 0;
 }
 
@@ -1657,7 +1660,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
        rmb();
        while (sw_cons != hw_cons) {
                unsigned int len;
-               u16 status;
+               u32 status;
                struct sw_bd *rx_buf;
                struct sk_buff *skb;
 
@@ -1673,7 +1676,7 @@ bnx2_rx_int(struct bnx2 *bp, int budget)
                rx_hdr = (struct l2_fhdr *) skb->data;
                len = rx_hdr->l2_fhdr_pkt_len - 4;
 
-               if (rx_hdr->l2_fhdr_errors &
+               if ((status = rx_hdr->l2_fhdr_status) &
                        (L2_FHDR_ERRORS_BAD_CRC |
                        L2_FHDR_ERRORS_PHY_DECODE |
                        L2_FHDR_ERRORS_ALIGNMENT |
@@ -1732,15 +1735,13 @@ reuse_rx:
 
                }
 
-               status = rx_hdr->l2_fhdr_status;
                skb->ip_summed = CHECKSUM_NONE;
                if (bp->rx_csum &&
                        (status & (L2_FHDR_STATUS_TCP_SEGMENT |
                        L2_FHDR_STATUS_UDP_DATAGRAM))) {
 
-                       u16 cksum = rx_hdr->l2_fhdr_tcp_udp_xsum;
-
-                       if (cksum == 0xffff)
+                       if (likely((status & (L2_FHDR_ERRORS_TCP_XSUM |
+                                             L2_FHDR_ERRORS_UDP_XSUM)) == 0))
                                skb->ip_summed = CHECKSUM_UNNECESSARY;
                }
 
@@ -2338,7 +2339,6 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
                        val |= BNX2_EMAC_MODE_PORT_MII |
                               BNX2_EMAC_MODE_MPKT_RCVD |
                               BNX2_EMAC_MODE_ACPI_RCVD |
-                              BNX2_EMAC_MODE_FORCE_LINK |
                               BNX2_EMAC_MODE_MPKT;
 
                        REG_WR(bp, BNX2_EMAC_MODE, val);
@@ -2374,7 +2374,8 @@ bnx2_set_power_state(struct bnx2 *bp, pci_power_t state)
                        wol_msg = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
                }
 
-               bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg);
+               if (!(bp->flags & NO_WOL_FLAG))
+                       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT3 | wol_msg, 0);
 
                pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
                if ((CHIP_ID(bp) == CHIP_ID_5706_A0) ||
@@ -3014,16 +3015,14 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
        val = REG_RD(bp, BNX2_MISC_ENABLE_CLR_BITS);
        udelay(5);
 
+       /* Wait for the firmware to tell us it is ok to issue a reset. */
+       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1);
+
        /* Deposit a driver reset signature so the firmware knows that
         * this is a soft reset. */
        REG_WR_IND(bp, bp->shmem_base + BNX2_DRV_RESET_SIGNATURE,
                   BNX2_DRV_RESET_SIGNATURE_MAGIC);
 
-       bp->fw_timed_out = 0;
-
-       /* Wait for the firmware to tell us it is ok to issue a reset. */
-       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code);
-
        /* Do a dummy read to force the chip to complete all current transaction
         * before we issue a reset. */
        val = REG_RD(bp, BNX2_MISC_ID);
@@ -3062,10 +3061,10 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
                return -ENODEV;
        }
 
-       bp->fw_timed_out = 0;
-
        /* Wait for the firmware to finish its initialization. */
-       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code);
+       rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT1 | reset_code, 0);
+       if (rc)
+               return rc;
 
        if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
                /* Adjust the voltage regular to two steps lower.  The default
@@ -3083,6 +3082,7 @@ static int
 bnx2_init_chip(struct bnx2 *bp)
 {
        u32 val;
+       int rc;
 
        /* Make sure the interrupt is not active. */
        REG_WR(bp, BNX2_PCICFG_INT_ACK_CMD, BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
@@ -3098,7 +3098,7 @@ bnx2_init_chip(struct bnx2 *bp)
 
        val |= (0x2 << 20) | (1 << 11);
 
-       if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz = 133))
+       if ((bp->flags & PCIX_FLAG) && (bp->bus_speed_mhz == 133))
                val |= (1 << 23);
 
        if ((CHIP_NUM(bp) == CHIP_NUM_5706) &&
@@ -3225,14 +3225,15 @@ bnx2_init_chip(struct bnx2 *bp)
        /* Initialize the receive filter. */
        bnx2_set_rx_mode(bp->dev);
 
-       bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET);
+       rc = bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT2 | BNX2_DRV_MSG_CODE_RESET,
+                         0);
 
        REG_WR(bp, BNX2_MISC_ENABLE_SET_BITS, 0x5ffffff);
        REG_RD(bp, BNX2_MISC_ENABLE_SET_BITS);
 
        udelay(20);
 
-       return 0;
+       return rc;
 }
 
 
@@ -3975,7 +3976,7 @@ bnx2_test_loopback(struct bnx2 *bp)
                pci_unmap_addr(rx_buf, mapping),
                bp->rx_buf_size, PCI_DMA_FROMDEVICE);
 
-       if (rx_hdr->l2_fhdr_errors &
+       if (rx_hdr->l2_fhdr_status &
                (L2_FHDR_ERRORS_BAD_CRC |
                L2_FHDR_ERRORS_PHY_DECODE |
                L2_FHDR_ERRORS_ALIGNMENT |
@@ -4471,7 +4472,9 @@ bnx2_close(struct net_device *dev)
 
        bnx2_netif_stop(bp);
        del_timer_sync(&bp->timer);
-       if (bp->wol)
+       if (bp->flags & NO_WOL_FLAG)
+               reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
+       else if (bp->wol)
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
        else
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;
@@ -5633,6 +5636,9 @@ bnx2_init_board(struct pci_dev *pdev, struct net_device *dev)
                }
        }
 
+       if (CHIP_NUM(bp) == CHIP_NUM_5708)
+               bp->flags |= NO_WOL_FLAG;
+
        if (CHIP_ID(bp) == CHIP_ID_5706_A0) {
                bp->tx_quick_cons_trip_int =
                        bp->tx_quick_cons_trip;
@@ -5816,7 +5822,9 @@ bnx2_suspend(struct pci_dev *pdev, pm_message_t state)
        bnx2_netif_stop(bp);
        netif_device_detach(dev);
        del_timer_sync(&bp->timer);
-       if (bp->wol)
+       if (bp->flags & NO_WOL_FLAG)
+               reset_code = BNX2_DRV_MSG_CODE_UNLOAD;
+       else if (bp->wol)
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_WOL;
        else
                reset_code = BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL;