/*
* hardware specific access to control-lines
+ * ctrl:
+ * NAND_CNE: bit 0 -> ! bit 0 & 4
+ * NAND_CLE: bit 1 -> bit 1
+ * NAND_ALE: bit 2 -> bit 2
+ *
*/
-static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd)
+static void sharpsl_nand_hwcontrol(struct mtd_info *mtd, int cmd,
+ unsigned int ctrl)
{
- switch (cmd) {
- case NAND_CTL_SETCLE:
- writeb(readb(FLASHCTL) | FLCLE, FLASHCTL);
- break;
- case NAND_CTL_CLRCLE:
- writeb(readb(FLASHCTL) & ~FLCLE, FLASHCTL);
- break;
-
- case NAND_CTL_SETALE:
- writeb(readb(FLASHCTL) | FLALE, FLASHCTL);
- break;
- case NAND_CTL_CLRALE:
- writeb(readb(FLASHCTL) & ~FLALE, FLASHCTL);
- break;
-
- case NAND_CTL_SETNCE:
- writeb(readb(FLASHCTL) & ~(FLCE0 | FLCE1), FLASHCTL);
- break;
- case NAND_CTL_CLRNCE:
- writeb(readb(FLASHCTL) | (FLCE0 | FLCE1), FLASHCTL);
- break;
+ struct nand_chip *chip = mtd->priv;
+
+ if (ctrl & NAND_CTRL_CHANGE) {
+ unsigned char bits = ctrl & 0x07;
+
+ bits |= (ctrl & 0x01) << 4;
+
+ bits ^= 0x11;
+
+ writeb((readb(FLASHCTL) & ~0x17) | bits, FLASHCTL);
}
+
+ if (cmd != NAND_CMD_NONE)
+ writeb(cmd, chip->IO_ADDR_W);
}
static uint8_t scan_ff_pattern[] = { 0xff, 0xff };
.pattern = scan_ff_pattern
};
-static struct nand_oobinfo akita_oobinfo = {
- .useecc = MTD_NANDECC_AUTOPLACE,
+static struct nand_ecclayout akita_oobinfo = {
.eccbytes = 24,
.eccpos = {
0x5, 0x1, 0x2, 0x3, 0x6, 0x7, 0x15, 0x11,
/*
* Main initialization routine
*/
-int __init sharpsl_nand_init(void)
+static int __init sharpsl_nand_init(void)
{
struct nand_chip *this;
struct mtd_partition *sharpsl_partition_info;
return -ENOMEM;
}
- /* map physical adress */
+ /* map physical address */
sharpsl_io_base = ioremap(sharpsl_phys_base, 0x1000);
if (!sharpsl_io_base) {
printk("ioremap to access Sharp SL NAND chip failed\n");
this->IO_ADDR_R = FLASHIO;
this->IO_ADDR_W = FLASHIO;
/* Set address of hardware control function */
- this->hwcontrol = sharpsl_nand_hwcontrol;
+ this->cmd_ctrl = sharpsl_nand_hwcontrol;
this->dev_ready = sharpsl_nand_dev_ready;
/* 15 us command delay time */
this->chip_delay = 15;
/* set eccmode using hardware ECC */
- this->eccmode = NAND_ECC_HW3_256;
+ this->ecc.mode = NAND_ECC_HW;
+ this->ecc.size = 256;
+ this->ecc.bytes = 3;
this->badblock_pattern = &sharpsl_bbt;
if (machine_is_akita() || machine_is_borzoi()) {
this->badblock_pattern = &sharpsl_akita_bbt;
- this->autooob = &akita_oobinfo;
+ this->ecc.layout = &akita_oobinfo;
}
- this->enable_hwecc = sharpsl_nand_enable_hwecc;
- this->calculate_ecc = sharpsl_nand_calculate_ecc;
- this->correct_data = nand_correct_data;
+ this->ecc.hwctl = sharpsl_nand_enable_hwecc;
+ this->ecc.calculate = sharpsl_nand_calculate_ecc;
+ this->ecc.correct = nand_correct_data;
/* Scan to find existence of the device */
err = nand_scan(sharpsl_mtd, 1);
}
}
- if (machine_is_husky() || machine_is_borzoi() || machine_is_akita()) {
- /* Need to use small eraseblock size for backward compatibility */
- sharpsl_mtd->flags |= MTD_NO_VIRTBLOCKS;
- }
-
add_mtd_partitions(sharpsl_mtd, sharpsl_partition_info, nr_partitions);
/* Return happy */
/*
* Clean up routine
*/
-#ifdef MODULE
static void __exit sharpsl_nand_cleanup(void)
{
- struct nand_chip *this = (struct nand_chip *)&sharpsl_mtd[1];
-
/* Release resources, unregister device */
nand_release(sharpsl_mtd);
}
module_exit(sharpsl_nand_cleanup);
-#endif
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Richard Purdie <rpurdie@rpsys.net>");