}
DBG("blksz %04x blks %04x flags %08x\n",
- 1 << data->blksz_bits, data->blocks, data->flags);
+ data->blksz, data->blocks, data->flags);
DBG("tsac %d ms nsac %d clk\n",
data->timeout_ns / 1000000, data->timeout_clks);
writew(mode, host->ioaddr + SDHCI_TRANSFER_MODE);
- writew(1 << data->blksz_bits, host->ioaddr + SDHCI_BLOCK_SIZE);
+ writew(data->blksz, host->ioaddr + SDHCI_BLOCK_SIZE);
writew(data->blocks, host->ioaddr + SDHCI_BLOCK_COUNT);
if (host->flags & SDHCI_USE_DMA) {
writel(sg_dma_address(data->sg), host->ioaddr + SDHCI_DMA_ADDRESS);
} else {
- host->size = (1 << data->blksz_bits) * data->blocks;
+ host->size = data->blksz * data->blocks;
host->cur_sg = data->sg;
host->num_sg = data->sg_len;
blocks = 0;
else
blocks = readw(host->ioaddr + SDHCI_BLOCK_COUNT);
- data->bytes_xfered = (1 << data->blksz_bits) * (data->blocks - blocks);
+ data->bytes_xfered = data->blksz * (data->blocks - blocks);
if ((data->error == MMC_ERR_NONE) && blocks) {
printk(KERN_ERR "%s: Controller signalled completion even "
static void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd)
{
int flags;
- u32 present;
- unsigned long max_jiffies;
+ unsigned long timeout;
WARN_ON(host->cmd);
DBG("Sending cmd (%x)\n", cmd->opcode);
/* Wait max 10 ms */
- max_jiffies = jiffies + (HZ + 99)/100;
- do {
- if (time_after(jiffies, max_jiffies)) {
+ timeout = 10;
+ while (readl(host->ioaddr + SDHCI_PRESENT_STATE) &
+ (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
+ if (timeout == 0) {
printk(KERN_ERR "%s: Controller never released "
"inhibit bits. Please report this to "
BUGMAIL ".\n", mmc_hostname(host->mmc));
tasklet_schedule(&host->finish_tasklet);
return;
}
- present = readl(host->ioaddr + SDHCI_PRESENT_STATE);
- } while (present & (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT));
+ timeout--;
+ mdelay(1);
+ }
mod_timer(&host->timer, jiffies + 10 * HZ);
{
int div;
u16 clk;
- unsigned long max_jiffies;
+ unsigned long timeout;
if (clock == host->clock)
return;
writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
/* Wait max 10 ms */
- max_jiffies = jiffies + (HZ + 99)/100;
- do {
- if (time_after(jiffies, max_jiffies)) {
+ timeout = 10;
+ while (!((clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL))
+ & SDHCI_CLOCK_INT_STABLE)) {
+ if (timeout == 0) {
printk(KERN_ERR "%s: Internal clock never stabilised. "
"Please report this to " BUGMAIL ".\n",
mmc_hostname(host->mmc));
sdhci_dumpregs(host);
return;
}
- clk = readw(host->ioaddr + SDHCI_CLOCK_CONTROL);
- } while (!(clk & SDHCI_CLOCK_INT_STABLE));
+ timeout--;
+ mdelay(1);
+ }
clk |= SDHCI_CLOCK_CARD_EN;
writew(clk, host->ioaddr + SDHCI_CLOCK_CONTROL);
host->clock = clock;
}
+static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
+{
+ u8 pwr;
+
+ if (host->power == power)
+ return;
+
+ writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
+
+ if (power == (unsigned short)-1)
+ goto out;
+
+ pwr = SDHCI_POWER_ON;
+
+ switch (power) {
+ case MMC_VDD_170:
+ case MMC_VDD_180:
+ case MMC_VDD_190:
+ pwr |= SDHCI_POWER_180;
+ break;
+ case MMC_VDD_290:
+ case MMC_VDD_300:
+ case MMC_VDD_310:
+ pwr |= SDHCI_POWER_300;
+ break;
+ case MMC_VDD_320:
+ case MMC_VDD_330:
+ case MMC_VDD_340:
+ pwr |= SDHCI_POWER_330;
+ break;
+ default:
+ BUG();
+ }
+
+ writeb(pwr, host->ioaddr + SDHCI_POWER_CONTROL);
+
+out:
+ host->power = power;
+}
+
/*****************************************************************************\
* *
* MMC callbacks *
sdhci_set_clock(host, ios->clock);
if (ios->power_mode == MMC_POWER_OFF)
- writeb(0, host->ioaddr + SDHCI_POWER_CONTROL);
+ sdhci_set_power(host, -1);
else
- writeb(0xFF, host->ioaddr + SDHCI_POWER_CONTROL);
+ sdhci_set_power(host, ios->vdd);
ctrl = readb(host->ioaddr + SDHCI_HOST_CONTROL);
if (ios->bus_width == MMC_BUS_WIDTH_4)
else /* XXX: Hack to get MMC layer to avoid highmem */
pdev->dma_mask = 0;
- host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+ host->max_clk =
+ (caps & SDHCI_CLOCK_BASE_MASK) >> SDHCI_CLOCK_BASE_SHIFT;
+ if (host->max_clk == 0) {
+ printk(KERN_ERR "%s: Hardware doesn't specify base clock "
+ "frequency.\n", host->slot_descr);
+ ret = -ENODEV;
+ goto unmap;
+ }
host->max_clk *= 1000000;
/*
mmc->ops = &sdhci_ops;
mmc->f_min = host->max_clk / 256;
mmc->f_max = host->max_clk;
- mmc->ocr_avail = MMC_VDD_32_33|MMC_VDD_33_34;
mmc->caps = MMC_CAP_4_BIT_DATA;
+ mmc->ocr_avail = 0;
+ if (caps & SDHCI_CAN_VDD_330)
+ mmc->ocr_avail |= MMC_VDD_32_33|MMC_VDD_33_34;
+ else if (caps & SDHCI_CAN_VDD_300)
+ mmc->ocr_avail |= MMC_VDD_29_30|MMC_VDD_30_31;
+ else if (caps & SDHCI_CAN_VDD_180)
+ mmc->ocr_avail |= MMC_VDD_17_18|MMC_VDD_18_19;
+
+ if (mmc->ocr_avail == 0) {
+ printk(KERN_ERR "%s: Hardware doesn't report any "
+ "support voltages.\n", host->slot_descr);
+ ret = -ENODEV;
+ goto unmap;
+ }
+
spin_lock_init(&host->lock);
/*
ret = request_irq(host->irq, sdhci_irq, SA_SHIRQ,
host->slot_descr, host);
if (ret)
- goto unmap;
+ goto untasklet;
sdhci_init(host);
return 0;
-unmap:
+untasklet:
tasklet_kill(&host->card_tasklet);
tasklet_kill(&host->finish_tasklet);
-
+unmap:
iounmap(host->ioaddr);
release:
pci_release_region(pdev, host->bar);
const struct pci_device_id *ent)
{
int ret, i;
- u8 slots;
+ u8 slots, rev;
struct sdhci_chip *chip;
BUG_ON(pdev == NULL);
BUG_ON(ent == NULL);
- DBG("found at %s\n", pci_name(pdev));
+ pci_read_config_byte(pdev, PCI_CLASS_REVISION, &rev);
+
+ printk(KERN_INFO DRIVER_NAME
+ ": SDHCI controller found at %s [%04x:%04x] (rev %x)\n",
+ pci_name(pdev), (int)pdev->vendor, (int)pdev->device,
+ (int)rev);
ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots);
if (ret)