static int mmc_omap_get_dma_channel(struct mmc_omap_host *host, struct mmc_data *data)
{
- const char *dev_name;
+ const char *dma_dev_name;
int sync_dev, dma_ch, is_read, r;
is_read = !(data->flags & MMC_DATA_WRITE);
if (is_read) {
if (host->id == 1) {
sync_dev = OMAP_DMA_MMC_RX;
- dev_name = "MMC1 read";
+ dma_dev_name = "MMC1 read";
} else {
sync_dev = OMAP_DMA_MMC2_RX;
- dev_name = "MMC2 read";
+ dma_dev_name = "MMC2 read";
}
} else {
if (host->id == 1) {
sync_dev = OMAP_DMA_MMC_TX;
- dev_name = "MMC1 write";
+ dma_dev_name = "MMC1 write";
} else {
sync_dev = OMAP_DMA_MMC2_TX;
- dev_name = "MMC2 write";
+ dma_dev_name = "MMC2 write";
}
}
- r = omap_request_dma(sync_dev, dev_name, mmc_omap_dma_cb,
+ r = omap_request_dma(sync_dev, dma_dev_name, mmc_omap_dma_cb,
host, &dma_ch);
if (r != 0) {
dev_dbg(mmc_dev(host->mmc), "omap_request_dma() failed with %d\n", r);
OMAP_MMC_WRITE(host, CON, dsor);
slot->saved_con = dsor;
if (ios->power_mode == MMC_POWER_ON) {
+ /* worst case at 400kHz, 80 cycles makes 200 microsecs */
+ int usecs = 250;
+
/* Send clock cycles, poll completion */
OMAP_MMC_WRITE(host, IE, 0);
OMAP_MMC_WRITE(host, STAT, 0xffff);
OMAP_MMC_WRITE(host, CMD, 1 << 7);
- while ((OMAP_MMC_READ(host, STAT) & 1) == 0);
+ while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) {
+ udelay(1);
+ usecs--;
+ }
OMAP_MMC_WRITE(host, STAT, 1);
}
host->slots[id] = slot;
- mmc->caps = MMC_CAP_MULTIWRITE;
+ mmc->caps = 0;
if (host->pdata->conf.wire4)
mmc->caps |= MMC_CAP_4_BIT_DATA;