#include <linux/mmc/host.h>
#include <linux/amba/bus.h>
#include <linux/clk.h>
+#include <linux/scatterlist.h>
#include <asm/cacheflush.h>
#include <asm/div64.h>
#include <asm/io.h>
-#include <asm/scatterlist.h>
#include <asm/sizes.h>
#include <asm/mach/mmc.h>
* partially written to a page is properly coherent.
*/
if (host->sg_len && data->flags & MMC_DATA_READ)
- flush_dcache_page(host->sg_ptr->page);
+ flush_dcache_page(sg_page(host->sg_ptr));
}
if (status & MCI_DATAEND) {
mmci_stop_data(host);
void __iomem *base = host->base;
char *ptr = buffer;
u32 status;
+ int host_remain = host->size;
do {
- int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
+ int count = host_remain - (readl(base + MMCIFIFOCNT) << 2);
if (count > remain)
count = remain;
ptr += count;
remain -= count;
+ host_remain -= count;
if (remain == 0)
break;
* page, ensure that the data cache is coherent.
*/
if (status & MCI_RXACTIVE)
- flush_dcache_page(host->sg_ptr->page);
+ flush_dcache_page(sg_page(host->sg_ptr));
if (!mmci_next_sg(host))
break;
host->cclk = host->mclk;
} else {
clk = host->mclk / (2 * ios->clock) - 1;
- if (clk > 256)
+ if (clk >= 256)
clk = 255;
host->cclk = host->mclk / (2 * (clk + 1));
}
host->plat = plat;
host->mclk = clk_get_rate(host->clk);
+ /*
+ * According to the spec, mclk is max 100 MHz,
+ * so we try to adjust the clock down to this,
+ * (if possible).
+ */
+ if (host->mclk > 100000000) {
+ ret = clk_set_rate(host->clk, 100000000);
+ if (ret < 0)
+ goto clk_disable;
+ host->mclk = clk_get_rate(host->clk);
+ DBG(host, "eventual mclk rate: %u Hz\n", host->mclk);
+ }
host->mmc = mmc;
host->base = ioremap(dev->res.start, SZ_4K);
if (!host->base) {