.cnt2_reg = DMA2_CNT2,
},
[SRAM_CH03] = {
- .name = "ch3",
- .cmds_start = 0x0,
- .ctrl_start = 0x0,
- .cdt = 0x0,
- .fifo_start = 0x0,
- .fifo_size = 0x0,
+ .name = "TS1 B",
+ .cmds_start = 0x100A0,
+ .ctrl_start = 0x10780,
+ .cdt = 0x10400,
+ .fifo_start = 0x5000,
+ .fifo_size = 0x1000,
.ptr1_reg = DMA3_PTR1,
.ptr2_reg = DMA3_PTR2,
.cnt1_reg = DMA3_CNT1,
[ RISC_WRITECR >> 28 ] = "writecr",
};
static int incr[16] = {
- [ RISC_WRITE >> 28 ] = 3, // 2
- [ RISC_JUMP >> 28 ] = 3, // 2
+ [ RISC_WRITE >> 28 ] = 3,
+ [ RISC_JUMP >> 28 ] = 3,
[ RISC_SKIP >> 28 ] = 1,
[ RISC_SYNC >> 28 ] = 1,
[ RISC_WRITERM >> 28 ] = 3,
break;
buf = list_entry(q->active.next,
struct cx23885_buffer, vb.queue);
+
/* count comes from the hw and is is 16bit wide --
* this trick handles wrap-arounds correctly for
* up to 32767 buffers in flight... */
if ((s16) (count - buf->count) < 0)
break;
+
do_gettimeofday(&buf->vb.ts);
dprintk(2, "[%p/%d] wakeup reg=%d buf=%d\n", buf, buf->vb.i,
count, buf->count);
cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH01 ], 188*4, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH02 ], 128, 0);
- cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 128, 0);
+ cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH03 ], 188*4, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH04 ], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH05 ], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH06 ], 188*4, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH08 ], 128, 0);
cx23885_sram_channel_setup(dev, &dev->sram_channels[ SRAM_CH09 ], 128, 0);
- switch(dev->board) {
- case CX23885_BOARD_HAUPPAUGE_HVR1250:
- /* GPIO-0 cx24227 demodulator reset */
- dprintk( 1, "%s() Configuring HVR1250 GPIO's\n", __FUNCTION__);
- cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
- break;
- case CX23885_BOARD_HAUPPAUGE_HVR1800:
- /* GPIO-0 656_CLK */
- /* GPIO-1 656_D0 */
- /* GPIO-2 8295A Reset */
- /* GPIO-3-10 cx23417 data0-7 */
- /* GPIO-11-14 cx23417 addr0-3 */
- /* GPIO-15-18 cx23417 READY, CS, RD, WR */
- /* GPIO-19 IR_RX */
- dprintk( 1, "%s() Configuring HVR1800 GPIO's\n", __FUNCTION__);
- // FIXME: Analog requires the tuner is brought out of reset
- break;
- }
+ cx23885_gpio_setup(dev);
}
{
dprintk(1, "%s()\n", __FUNCTION__);
+ /* The cx23885 bridge has a weird bug which causes NMI to be asserted
+ * when DMA begins if RDR_TLCTL0 bit4 is not cleared. It does not
+ * occur on the cx23887 bridge.
+ */
if(dev->bridge == CX23885_BRIDGE_885)
cx_clear(RDR_TLCTL0, 1 << 4);
int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc,
u32 reg, u32 mask, u32 value);
-static int cx23885_ir_init(struct cx23885_dev *dev)
+static int cx23885_init_tsport(struct cx23885_dev *dev, struct cx23885_tsport *port, int portno)
{
- dprintk(1, "%s()\n", __FUNCTION__);
-
- switch (dev->board) {
- case CX23885_BOARD_HAUPPAUGE_HVR1250:
- case CX23885_BOARD_HAUPPAUGE_HVR1800:
- dprintk(1, "%s() FIXME - Implement IR support\n", __FUNCTION__);
+ dprintk(1, "%s(portno=%d)\n", __FUNCTION__, portno);
+
+ /* Transport bus init dma queue - Common settings */
+ port->dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
+ port->ts_int_msk_val = 0x1111; /* TS port bits for RISC */
+
+ spin_lock_init(&port->slock);
+ port->dev = dev;
+ port->nr = portno;
+
+ INIT_LIST_HEAD(&port->mpegq.active);
+ INIT_LIST_HEAD(&port->mpegq.queued);
+ port->mpegq.timeout.function = cx23885_timeout;
+ port->mpegq.timeout.data = (unsigned long)port;
+ init_timer(&port->mpegq.timeout);
+
+ switch(portno) {
+ case 1:
+ port->reg_gpcnt = VID_B_GPCNT;
+ port->reg_gpcnt_ctl = VID_B_GPCNT_CTL;
+ port->reg_dma_ctl = VID_B_DMA_CTL;
+ port->reg_lngth = VID_B_LNGTH;
+ port->reg_hw_sop_ctrl = VID_B_HW_SOP_CTL;
+ port->reg_gen_ctrl = VID_B_GEN_CTL;
+ port->reg_bd_pkt_status = VID_B_BD_PKT_STATUS;
+ port->reg_sop_status = VID_B_SOP_STATUS;
+ port->reg_fifo_ovfl_stat = VID_B_FIFO_OVFL_STAT;
+ port->reg_vld_misc = VID_B_VLD_MISC;
+ port->reg_ts_clk_en = VID_B_TS_CLK_EN;
+ port->reg_src_sel = VID_B_SRC_SEL;
+ port->reg_ts_int_msk = VID_B_INT_MSK;
+ port->reg_ts_int_stat = VID_B_INT_STAT;
+ port->sram_chno = SRAM_CH03; /* VID_B */
+ port->pci_irqmask = 0x02; /* VID_B bit1 */
break;
+ case 2:
+ port->reg_gpcnt = VID_C_GPCNT;
+ port->reg_gpcnt_ctl = VID_C_GPCNT_CTL;
+ port->reg_dma_ctl = VID_C_DMA_CTL;
+ port->reg_lngth = VID_C_LNGTH;
+ port->reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
+ port->reg_gen_ctrl = VID_C_GEN_CTL;
+ port->reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
+ port->reg_sop_status = VID_C_SOP_STATUS;
+ port->reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
+ port->reg_vld_misc = VID_C_VLD_MISC;
+ port->reg_ts_clk_en = VID_C_TS_CLK_EN;
+ port->reg_src_sel = 0;
+ port->reg_ts_int_msk = VID_C_INT_MSK;
+ port->reg_ts_int_stat = VID_C_INT_STAT;
+ port->sram_chno = SRAM_CH06; /* VID_C */
+ port->pci_irqmask = 0x04; /* VID_C bit2 */
+ break;
+ default:
+ BUG();
}
+ cx23885_risc_stopper(dev->pci, &port->mpegq.stopper,
+ port->reg_dma_ctl, port->dma_ctl_val, 0x00);
+
return 0;
}
atomic_inc(&dev->refcount);
dev->nr = cx23885_devcount++;
+ sprintf(dev->name, "cx23885[%d]", dev->nr);
+
+ mutex_lock(&devlist);
+ list_add_tail(&dev->devlist, &cx23885_devlist);
+ mutex_unlock(&devlist);
+
+ /* Configure the internal memory */
+ if(dev->pci->device == 0x8880) {
+ dev->bridge = CX23885_BRIDGE_887;
+ dev->sram_channels = cx23887_sram_channels;
+ } else
+ if(dev->pci->device == 0x8852) {
+ dev->bridge = CX23885_BRIDGE_885;
+ dev->sram_channels = cx23885_sram_channels;
+ } else
+ BUG();
+
+ dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
+ __FUNCTION__, dev->bridge);
+
+ /* board config */
+ dev->board = UNSET;
+ if (card[dev->nr] < cx23885_bcount)
+ dev->board = card[dev->nr];
+ for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
+ if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
+ dev->pci->subsystem_device == cx23885_subids[i].subdevice)
+ dev->board = cx23885_subids[i].card;
+ if (UNSET == dev->board) {
+ dev->board = CX23885_BOARD_UNKNOWN;
+ cx23885_card_list(dev);
+ }
+
dev->pci_bus = dev->pci->bus->number;
dev->pci_slot = PCI_SLOT(dev->pci->devfn);
dev->pci_irqmask = 0x001f00;
dev->i2c_bus[2].reg_wdata = I2C3_WDATA;
dev->i2c_bus[2].i2c_period = (0x07 << 24); /* 1.95MHz */
- /* Transport bus init dma queue */
- spin_lock_init(&dev->ts2.slock);
- dev->ts2.dev = dev;
- dev->ts2.nr = 2;
- dev->ts2.sram_chno = SRAM_CH06;
- INIT_LIST_HEAD(&dev->ts2.mpegq.active);
- INIT_LIST_HEAD(&dev->ts2.mpegq.queued);
- dev->ts2.mpegq.timeout.function = cx23885_timeout;
- dev->ts2.mpegq.timeout.data = (unsigned long)&dev->ts2;
- init_timer(&dev->ts2.mpegq.timeout);
-
- dev->ts2.reg_gpcnt = VID_C_GPCNT;
- dev->ts2.reg_gpcnt_ctl = VID_C_GPCNT_CTL;
- dev->ts2.reg_dma_ctl = VID_C_DMA_CTL;
- dev->ts2.reg_lngth = VID_C_LNGTH;
- dev->ts2.reg_hw_sop_ctrl = VID_C_HW_SOP_CTL;
- dev->ts2.reg_gen_ctrl = VID_C_GEN_CTL;
- dev->ts2.reg_bd_pkt_status = VID_C_BD_PKT_STATUS;
- dev->ts2.reg_sop_status = VID_C_SOP_STATUS;
- dev->ts2.reg_fifo_ovfl_stat = VID_C_FIFO_OVFL_STAT;
- dev->ts2.reg_vld_misc = VID_C_VLD_MISC;
- dev->ts2.reg_ts_clk_en = VID_C_TS_CLK_EN;
- dev->ts2.reg_ts_int_msk = VID_C_INT_MSK;
-
- // FIXME: Make this board specific
- dev->ts2.pci_irqmask = 0x04; /* TS Port 2 bit */
- dev->ts2.dma_ctl_val = 0x11; /* Enable RISC controller and Fifo */
- dev->ts2.ts_int_msk_val = 0x1111; /* TS port bits for RISC */
- dev->ts2.gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
- dev->ts2.ts_clk_en_val = 0x1; /* Enable TS_CLK */
-
- cx23885_risc_stopper(dev->pci, &dev->ts2.mpegq.stopper,
- dev->ts2.reg_dma_ctl, dev->ts2.dma_ctl_val, 0x00);
+ if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
+ cx23885_init_tsport(dev, &dev->ts1, 1);
- sprintf(dev->name, "cx23885[%d]", dev->nr);
+ if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
+ cx23885_init_tsport(dev, &dev->ts2, 2);
if (get_resources(dev) < 0) {
printk(KERN_ERR "CORE %s No more PCIe resources for "
goto fail_free;
}
- mutex_lock(&devlist);
- list_add_tail(&dev->devlist, &cx23885_devlist);
- mutex_unlock(&devlist);
-
/* PCIe stuff */
dev->lmmio = ioremap(pci_resource_start(dev->pci,0),
pci_resource_len(dev->pci,0));
dev->bmmio = (u8 __iomem *)dev->lmmio;
- /* board config */
- dev->board = UNSET;
- if (card[dev->nr] < cx23885_bcount)
- dev->board = card[dev->nr];
- for (i = 0; UNSET == dev->board && i < cx23885_idcount; i++)
- if (dev->pci->subsystem_vendor == cx23885_subids[i].subvendor &&
- dev->pci->subsystem_device == cx23885_subids[i].subdevice)
- dev->board = cx23885_subids[i].card;
- if (UNSET == dev->board) {
- dev->board = CX23885_BOARD_UNKNOWN;
- cx23885_card_list(dev);
- }
printk(KERN_INFO "CORE %s: subsystem: %04x:%04x, board: %s [card=%d,%s]\n",
dev->name, dev->pci->subsystem_vendor,
dev->pci->subsystem_device, cx23885_boards[dev->board].name,
dev->board, card[dev->nr] == dev->board ?
"insmod option" : "autodetected");
- /* Configure the internal memory */
- if(dev->pci->device == 0x8880) {
- dev->bridge = CX23885_BRIDGE_887;
- dev->sram_channels = cx23887_sram_channels;
- } else
- if(dev->pci->device == 0x8852) {
- dev->bridge = CX23885_BRIDGE_885;
- dev->sram_channels = cx23885_sram_channels;
- }
- dprintk(1, "%s() Memory configured for PCIe bridge type %d\n",
- __FUNCTION__, dev->bridge);
-
cx23885_pci_quirks(dev);
/* init hardware */
cx23885_i2c_register(&dev->i2c_bus[1]);
cx23885_i2c_register(&dev->i2c_bus[2]);
cx23885_call_i2c_clients (&dev->i2c_bus[0], TUNER_SET_STANDBY, NULL);
-
cx23885_card_setup(dev);
cx23885_ir_init(dev);
- if (cx23885_dvb_register(&dev->ts2) < 0) {
- printk(KERN_ERR "%s() Failed to register dvb adapters\n",
- __FUNCTION__);
+ if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB) {
+ if (cx23885_dvb_register(&dev->ts1) < 0) {
+ printk(KERN_ERR "%s() Failed to register dvb adapters on VID_B\n",
+ __FUNCTION__);
+ }
+ }
+
+ if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB) {
+ if (cx23885_dvb_register(&dev->ts2) < 0) {
+ printk(KERN_ERR "%s() Failed to register dvb adapters on VID_C\n",
+ __FUNCTION__);
+ }
}
return 0;
if (!atomic_dec_and_test(&dev->refcount))
return;
- cx23885_dvb_unregister(&dev->ts2);
+ if(cx23885_boards[dev->board].portb == CX23885_MPEG_DVB)
+ cx23885_dvb_unregister(&dev->ts1);
+
+ if(cx23885_boards[dev->board].portc == CX23885_MPEG_DVB)
+ cx23885_dvb_unregister(&dev->ts2);
+
cx23885_i2c_unregister(&dev->i2c_bus[2]);
cx23885_i2c_unregister(&dev->i2c_bus[1]);
cx23885_i2c_unregister(&dev->i2c_bus[0]);
/* write and jump need and extra dword */
instructions = fields * (1 + ((bpl + padding) * lines) / PAGE_SIZE + lines);
instructions += 2;
- //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
return rc;
instructions = 1 + (bpl * lines) / PAGE_SIZE + lines;
instructions += 1;
- //if ((rc = btcx_riscmem_alloc(pci,risc,instructions*8)) < 0)
if ((rc = btcx_riscmem_alloc(pci,risc,instructions*12)) < 0)
return rc;
/* write risc instructions */
rp = risc->cpu;
- //*(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2 | RISC_IMM);
*(rp++) = cpu_to_le32(RISC_WRITECR | RISC_IRQ2);
*(rp++) = cpu_to_le32(reg);
*(rp++) = cpu_to_le32(value);
/* write TS length to chip */
cx_write(port->reg_lngth, buf->vb.width);
- if (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) {
- printk( "%s() Failed. Unsupported value in .portc (0x%08x)\n",
- __FUNCTION__, cx23885_boards[dev->board].portc );
+ if ( (!(cx23885_boards[dev->board].portb & CX23885_MPEG_DVB)) &&
+ (!(cx23885_boards[dev->board].portc & CX23885_MPEG_DVB)) ) {
+ printk( "%s() Failed. Unsupported value in .portb/c (0x%08x)/(0x%08x)\n",
+ __FUNCTION__,
+ cx23885_boards[dev->board].portb,
+ cx23885_boards[dev->board].portc );
return -EINVAL;
}
- // FIXME: review the need for these two lines
- dprintk( 1, "%s() doing .dvb\n", __FUNCTION__);
udelay(100);
+ /* If the port supports SRC SELECT, configure it */
+ if(port->reg_src_sel)
+ cx_write(port->reg_src_sel, port->src_sel_val);
+
cx_write(port->reg_hw_sop_ctrl, 0x47 << 16 | 188 << 4);
cx_write(port->reg_ts_clk_en, port->ts_clk_en_val);
-
- // FIXME: review the need for this
- cx_write(GPIO2, 0x00);
-
- switch (dev->board) {
- case CX23885_BOARD_HAUPPAUGE_HVR1250:
- case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
- case CX23885_BOARD_HAUPPAUGE_HVR1800:
- cx_write(port->reg_vld_misc, 0x00);
- dprintk(1, "%s() Configuring HVR1800/lp/1500 board\n",
- __FUNCTION__);
- break;
- default:
- // FIXME
- printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
- }
-
+ cx_write(port->reg_vld_misc, 0x00);
cx_write(port->reg_gen_ctrl, port->gen_ctrl_val);
udelay(100);
+ // NOTE: this is 2 (reserved) for portb, does it matter?
/* reset counter to zero */
cx_write(port->reg_gpcnt_ctl, 3);
q->count = 1;
cx_set(PCI_INT_MSK, dev->pci_irqmask | port->pci_irqmask);
break;
default:
- // FIXME: generate a sensible switch-default message
- printk(KERN_ERR "%s() error, default case", __FUNCTION__ );
+ BUG();
}
- dprintk(1, "%s() Register Dump\n", __FUNCTION__);
- dprintk(1, "%s() set port ts_int_msk, now %x\n", __FUNCTION__, cx_read(port->reg_ts_int_msk) );
- dprintk(1, "%s() DEV_CNTRL2 0x%08x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
- dprintk(1, "%s() PCI_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(PCI_INT_MSK) );
- dprintk(1, "%s() VID_A_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(VID_A_INT_MSK) );
- dprintk(1, "%s() VID_B_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(VID_B_INT_MSK) );
- dprintk(1, "%s() VID_C_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSK) );
- dprintk(1, "%s() VID_A_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(VID_A_DMA_CTL) );
- dprintk(1, "%s() VID_B_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(VID_B_DMA_CTL) );
- dprintk(1, "%s() VID_C_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
- dprintk(1, "%s() AUD_INT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_INT_INT_MSK) );
- dprintk(1, "%s() AUD_INT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_INT_DMA_CTL) );
- dprintk(1, "%s() AUD_EXT_INT_MSK 0x%08x\n", __FUNCTION__, cx_read(AUDIO_EXT_INT_MSK) );
- dprintk(1, "%s() AUD_EXT_DMA_CTL 0x%08x\n", __FUNCTION__, cx_read(AUD_EXT_DMA_CTL) );
-
cx_set(DEV_CNTRL2, (1<<5)); /* Enable RISC controller */
- dprintk(1, "%s() set dev_cntrl2, now %x\n", __FUNCTION__, cx_read(DEV_CNTRL2) );
- dprintk(1, "%s() VID_C_DMA_CTL , now %x\n", __FUNCTION__, cx_read(port->reg_dma_ctl) );
- dprintk(1, "%s() VID_C_DMA_CTL , now %x\n", __FUNCTION__, cx_read(VID_C_DMA_CTL) );
- dprintk(1, "%s() PAD_CTRL %x\n", __FUNCTION__, cx_read(PAD_CTRL) );
- dprintk(1, "%s() GPIO2 %x\n", __FUNCTION__, cx_read(GPIO2) );
- dprintk(1, "%s() VID_C_LN_LNGTH , now %x\n", __FUNCTION__, cx_read(port->reg_lngth) );
- dprintk(1, "%s() VID_C_HW_SOP_CTL, now %x\n", __FUNCTION__, cx_read(port->reg_hw_sop_ctrl) );
- dprintk(1, "%s() VID_C_GEN_CTL , now %x\n", __FUNCTION__, cx_read(port->reg_gen_ctrl) );
- dprintk(1, "%s() VID_C_SOP_STATUS, now %x\n", __FUNCTION__, cx_read(VID_C_SOP_STATUS) );
- dprintk(1, "%s() VID_C_TS_CLK_EN , now %x\n", __FUNCTION__, cx_read(VID_C_TS_CLK_EN) );
- dprintk(1, "%s() VID_C_FIFO_OVLST, now %x\n", __FUNCTION__, cx_read(VID_C_FIFO_OVFL_STAT) );
- dprintk(1, "%s() VID_C_INT_MSTAT , now 0x%08x\n", __FUNCTION__, cx_read(VID_C_INT_MSTAT) );
return 0;
}
mod_timer(&cx88q->timeout, jiffies + BUFFER_TIMEOUT);
dprintk(1, "[%p/%d] %s - first active\n",
buf, buf->vb.i, __FUNCTION__);
-
} else {
dprintk( 1, "queue is not empty - append to active\n" );
prev = list_entry(cx88q->active.prev, struct cx23885_buffer,
do_cancel_buffers(port, "timeout", 1);
}
-#define PCI_MSK_APB_DMA (1 << 12)
-#define PCI_MSK_AL_WR (1 << 11)
-#define PCI_MSK_AL_RD (1 << 10)
-#define PCI_MSK_RISC_WR (1 << 9)
-#define PCI_MSK_RISC_RD (1 << 8)
-
-#define PCI_MSK_AUD_EXT (1 << 4)
-#define PCI_MSK_AUD_INT (1 << 3)
-#define PCI_MSK_VID_C (1 << 2)
-#define PCI_MSK_VID_B (1 << 1)
-#define PCI_MSK_VID_A 1
-
-#define VID_C_MSK_BAD_PKT (1 << 20)
-#define VID_C_MSK_OPC_ERR (1 << 16)
-#define VID_C_MSK_SYNC (1 << 12)
-#define VID_C_MSK_OF (1 << 8)
-#define VID_C_MSK_RISCI2 (1 << 4)
-#define VID_C_MSK_RISCI1 1
+static int cx23885_irq_ts(struct cx23885_tsport *port, u32 status)
+{
+ struct cx23885_dev *dev = port->dev;
+ int handled = 0;
+ u32 count;
+
+ if ( (status & VID_BC_MSK_OPC_ERR) ||
+ (status & VID_BC_MSK_BAD_PKT) ||
+ (status & VID_BC_MSK_SYNC) ||
+ (status & VID_BC_MSK_OF))
+ {
+ if (status & VID_BC_MSK_OPC_ERR)
+ dprintk(7, " (VID_BC_MSK_OPC_ERR 0x%08x)\n", VID_BC_MSK_OPC_ERR);
+ if (status & VID_BC_MSK_BAD_PKT)
+ dprintk(7, " (VID_BC_MSK_BAD_PKT 0x%08x)\n", VID_BC_MSK_BAD_PKT);
+ if (status & VID_BC_MSK_SYNC)
+ dprintk(7, " (VID_BC_MSK_SYNC 0x%08x)\n", VID_BC_MSK_SYNC);
+ if (status & VID_BC_MSK_OF)
+ dprintk(7, " (VID_BC_MSK_OF 0x%08x)\n", VID_BC_MSK_OF);
+
+ printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
+
+ cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
+ cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
+
+ } else if (status & VID_BC_MSK_RISCI1) {
+
+ dprintk(7, " (RISCI1 0x%08x)\n", VID_BC_MSK_RISCI1);
+
+ spin_lock(&port->slock);
+ count = cx_read(port->reg_gpcnt);
+ cx23885_wakeup(port, &port->mpegq, count);
+ spin_unlock(&port->slock);
+
+ } else if (status & VID_BC_MSK_RISCI2) {
+
+ dprintk(7, " (RISCI2 0x%08x)\n", VID_BC_MSK_RISCI2);
+
+ spin_lock(&port->slock);
+ cx23885_restart_queue(port, &port->mpegq);
+ spin_unlock(&port->slock);
+
+ }
+ if (status) {
+ cx_write(port->reg_ts_int_stat, status);
+ handled = 1;
+ }
+
+ return handled;
+}
static irqreturn_t cx23885_irq(int irq, void *dev_id)
{
struct cx23885_dev *dev = dev_id;
- struct cx23885_tsport *port = &dev->ts2;
+ struct cx23885_tsport *ts1 = &dev->ts1;
+ struct cx23885_tsport *ts2 = &dev->ts2;
u32 pci_status, pci_mask;
+ u32 ts1_status, ts1_mask;
u32 ts2_status, ts2_mask;
- int count = 0, handled = 0;
+ int ts1_count = 0, ts2_count = 0, handled = 0;
pci_status = cx_read(PCI_INT_STAT);
pci_mask = cx_read(PCI_INT_MSK);
-
+ ts1_status = cx_read(VID_B_INT_STAT);
+ ts1_mask = cx_read(VID_B_INT_MSK);
ts2_status = cx_read(VID_C_INT_STAT);
ts2_mask = cx_read(VID_C_INT_MSK);
- if ( (pci_status == 0) && (ts2_status == 0) )
+ if ( (pci_status == 0) && (ts2_status == 0) && (ts1_status == 0) )
goto out;
- count = cx_read(port->reg_gpcnt);
+ ts1_count = cx_read(ts1->reg_gpcnt);
+ ts2_count = cx_read(ts2->reg_gpcnt);
dprintk(7, "pci_status: 0x%08x pci_mask: 0x%08x\n", pci_status, pci_mask );
- dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, count );
+ dprintk(7, "ts1_status: 0x%08x ts1_mask: 0x%08x count: 0x%x\n", ts1_status, ts1_mask, ts1_count );
+ dprintk(7, "ts2_status: 0x%08x ts2_mask: 0x%08x count: 0x%x\n", ts2_status, ts2_mask, ts2_count );
if ( (pci_status & PCI_MSK_RISC_RD) ||
(pci_status & PCI_MSK_RISC_WR) ||
}
- if ( (ts2_status & VID_C_MSK_OPC_ERR) ||
- (ts2_status & VID_C_MSK_BAD_PKT) ||
- (ts2_status & VID_C_MSK_SYNC) ||
- (ts2_status & VID_C_MSK_OF))
- {
- if (ts2_status & VID_C_MSK_OPC_ERR)
- dprintk(7, " (VID_C_MSK_OPC_ERR 0x%08x)\n", VID_C_MSK_OPC_ERR);
- if (ts2_status & VID_C_MSK_BAD_PKT)
- dprintk(7, " (VID_C_MSK_BAD_PKT 0x%08x)\n", VID_C_MSK_BAD_PKT);
- if (ts2_status & VID_C_MSK_SYNC)
- dprintk(7, " (VID_C_MSK_SYNC 0x%08x)\n", VID_C_MSK_SYNC);
- if (ts2_status & VID_C_MSK_OF)
- dprintk(7, " (VID_C_MSK_OF 0x%08x)\n", VID_C_MSK_OF);
-
- printk(KERN_ERR "%s: mpeg risc op code error\n", dev->name);
+ if (ts1_status)
+ handled += cx23885_irq_ts(ts1, ts1_status);
- cx_clear(port->reg_dma_ctl, port->dma_ctl_val);
- cx23885_sram_channel_dump(dev, &dev->sram_channels[ port->sram_chno ]);
-
- } else if (ts2_status & VID_C_MSK_RISCI1) {
-
- dprintk(7, " (RISCI1 0x%08x)\n", VID_C_MSK_RISCI1);
-
- spin_lock(&port->slock);
- count = cx_read(port->reg_gpcnt);
- cx23885_wakeup(port, &port->mpegq, count);
- spin_unlock(&port->slock);
-
- } else if (ts2_status & VID_C_MSK_RISCI2) {
-
- dprintk(7, " (RISCI2 0x%08x)\n", VID_C_MSK_RISCI2);
-
- spin_lock(&port->slock);
- cx23885_restart_queue(port, &port->mpegq);
- spin_unlock(&port->slock);
-
- }
+ if (ts2_status)
+ handled += cx23885_irq_ts(ts2, ts2_status);
- cx_write(VID_C_INT_STAT, ts2_status);
- cx_write(PCI_INT_STAT, pci_status);
- handled = 1;
+ if (handled)
+ cx_write(PCI_INT_STAT, pci_status);
out:
return IRQ_RETVAL(handled);
}
projects / linux-2.6 / blobdiff