/*
- * For the Realtek RTL chip RTL2831U
- * Realtek Release Date: 2008-03-14, ver 080314
- * Realtek version RTL2831 Linux driver version 080314
- * ver 080314
- *
- * for linux kernel version 2.6.21.4 - 2.6.22-14
- * support MXL5005s and MT2060 tuners (support tuner auto-detecting)
- * support two IR types -- RC5 and NEC
- *
- * Known boards with Realtek RTL chip RTL2821U
- * Freecom USB stick 14aa:0160 (version 4)
- * Conceptronic CTVDIGRCU
- *
- * Copyright (c) 2008 Realtek
- * Copyright (c) 2008 Jan Hoogenraad, Barnaby Shearer, Andy Hasper
- * This code is placed under the terms of the GNU General Public License
- *
- * Released by Realtek under GPLv2.
- * Thanks to Realtek for a lot of support we received !
- *
- * Revision: 080314 - original version
- */
+ MaxLinear MXL5005S VSB/QAM/DVBT tuner driver
+ Copyright (C) 2008 MaxLinear
+ Copyright (C) 2008 Steven Toth <stoth@hauppauge.com>
-#ifndef __MXL5005S_H
-#define __MXL5005S_H
-
-/*
- * The following context is source code provided by MaxLinear.
- * MaxLinear source code - Common.h
- */
-
-typedef void *HANDLE; /* Pointer to memory location */
-
-#define TUNER_REGS_NUM 104
-#define INITCTRL_NUM 40
-
-#ifdef _MXL_PRODUCTION
-#define CHCTRL_NUM 39
-#else
-#define CHCTRL_NUM 36
-#endif
-
-#define MXLCTRL_NUM 189
-#define MASTER_CONTROL_ADDR 9
-
-/* Enumeration of AGC Mode */
-typedef enum
-{
- MXL_DUAL_AGC = 0,
- MXL_SINGLE_AGC
-} AGC_Mode;
-
-/* Enumeration of Master Control Register State */
-typedef enum
-{
- MC_LOAD_START = 1,
- MC_POWER_DOWN,
- MC_SYNTH_RESET,
- MC_SEQ_OFF
-} Master_Control_State;
-
-/* Enumeration of MXL5005 Tuner Mode */
-typedef enum
-{
- MXL_ANALOG_MODE = 0,
- MXL_DIGITAL_MODE
-} Tuner_Mode;
-
-/* Enumeration of MXL5005 Tuner IF Mode */
-typedef enum
-{
- MXL_ZERO_IF = 0,
- MXL_LOW_IF
-} Tuner_IF_Mode;
-
-/* Enumeration of MXL5005 Tuner Clock Out Mode */
-typedef enum
-{
- MXL_CLOCK_OUT_DISABLE = 0,
- MXL_CLOCK_OUT_ENABLE
-} Tuner_Clock_Out;
-
-/* Enumeration of MXL5005 Tuner Div Out Mode */
-typedef enum
-{
- MXL_DIV_OUT_1 = 0,
- MXL_DIV_OUT_4
-
-} Tuner_Div_Out;
-
-/* Enumeration of MXL5005 Tuner Pull-up Cap Select Mode */
-typedef enum
-{
- MXL_CAP_SEL_DISABLE = 0,
- MXL_CAP_SEL_ENABLE
-
-} Tuner_Cap_Select;
-
-/* Enumeration of MXL5005 Tuner RSSI Mode */
-typedef enum
-{
- MXL_RSSI_DISABLE = 0,
- MXL_RSSI_ENABLE
-
-} Tuner_RSSI;
-
-/* Enumeration of MXL5005 Tuner Modulation Type */
-typedef enum
-{
- MXL_DEFAULT_MODULATION = 0,
- MXL_DVBT,
- MXL_ATSC,
- MXL_QAM,
- MXL_ANALOG_CABLE,
- MXL_ANALOG_OTA
-} Tuner_Modu_Type;
-
-/* Enumeration of MXL5005 Tuner Tracking Filter Type */
-typedef enum
-{
- MXL_TF_DEFAULT = 0,
- MXL_TF_OFF,
- MXL_TF_C,
- MXL_TF_C_H,
- MXL_TF_D,
- MXL_TF_D_L,
- MXL_TF_E,
- MXL_TF_F,
- MXL_TF_E_2,
- MXL_TF_E_NA,
- MXL_TF_G
-} Tuner_TF_Type;
-
-/* MXL5005 Tuner Register Struct */
-typedef struct _TunerReg_struct
-{
- u16 Reg_Num; /* Tuner Register Address */
- u16 Reg_Val; /* Current sofware programmed value waiting to be writen */
-} TunerReg_struct;
-
-/* MXL5005 Tuner Control Struct */
-typedef struct _TunerControl_struct {
- u16 Ctrl_Num; /* Control Number */
- u16 size; /* Number of bits to represent Value */
- u16 addr[25]; /* Array of Tuner Register Address for each bit position */
- u16 bit[25]; /* Array of bit position in Register Address for each bit position */
- u16 val[25]; /* Binary representation of Value */
-} TunerControl_struct;
-
-/* MXL5005 Tuner Struct */
-typedef struct _Tuner_struct
-{
- u8 Mode; /* 0: Analog Mode ; 1: Digital Mode */
- u8 IF_Mode; /* for Analog Mode, 0: zero IF; 1: low IF */
- u32 Chan_Bandwidth; /* filter channel bandwidth (6, 7, 8) */
- u32 IF_OUT; /* Desired IF Out Frequency */
- u16 IF_OUT_LOAD; /* IF Out Load Resistor (200/300 Ohms) */
- u32 RF_IN; /* RF Input Frequency */
- u32 Fxtal; /* XTAL Frequency */
- u8 AGC_Mode; /* AGC Mode 0: Dual AGC; 1: Single AGC */
- u16 TOP; /* Value: take over point */
- u8 CLOCK_OUT; /* 0: turn off clock out; 1: turn on clock out */
- u8 DIV_OUT; /* 4MHz or 16MHz */
- u8 CAPSELECT; /* 0: disable On-Chip pulling cap; 1: enable */
- u8 EN_RSSI; /* 0: disable RSSI; 1: enable RSSI */
- u8 Mod_Type; /* Modulation Type; */
- /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
- u8 TF_Type; /* Tracking Filter Type */
- /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
-
- /* Calculated Settings */
- u32 RF_LO; /* Synth RF LO Frequency */
- u32 IF_LO; /* Synth IF LO Frequency */
- u32 TG_LO; /* Synth TG_LO Frequency */
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
- /* Pointers to ControlName Arrays */
- u16 Init_Ctrl_Num; /* Number of INIT Control Names */
- TunerControl_struct
- Init_Ctrl[INITCTRL_NUM]; /* INIT Control Names Array Pointer */
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
- u16 CH_Ctrl_Num; /* Number of CH Control Names */
- TunerControl_struct
- CH_Ctrl[CHCTRL_NUM]; /* CH Control Name Array Pointer */
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- u16 MXL_Ctrl_Num; /* Number of MXL Control Names */
- TunerControl_struct
- MXL_Ctrl[MXLCTRL_NUM]; /* MXL Control Name Array Pointer */
+*/
- /* Pointer to Tuner Register Array */
- u16 TunerRegs_Num; /* Number of Tuner Registers */
- TunerReg_struct
- TunerRegs[TUNER_REGS_NUM]; /* Tuner Register Array Pointer */
-
-} Tuner_struct;
-
-typedef enum
-{
- /* Initialization Control Names */
- DN_IQTN_AMP_CUT = 1, /* 1 */
- BB_MODE, /* 2 */
- BB_BUF, /* 3 */
- BB_BUF_OA, /* 4 */
- BB_ALPF_BANDSELECT, /* 5 */
- BB_IQSWAP, /* 6 */
- BB_DLPF_BANDSEL, /* 7 */
- RFSYN_CHP_GAIN, /* 8 */
- RFSYN_EN_CHP_HIGAIN, /* 9 */
- AGC_IF, /* 10 */
- AGC_RF, /* 11 */
- IF_DIVVAL, /* 12 */
- IF_VCO_BIAS, /* 13 */
- CHCAL_INT_MOD_IF, /* 14 */
- CHCAL_FRAC_MOD_IF, /* 15 */
- DRV_RES_SEL, /* 16 */
- I_DRIVER, /* 17 */
- EN_AAF, /* 18 */
- EN_3P, /* 19 */
- EN_AUX_3P, /* 20 */
- SEL_AAF_BAND, /* 21 */
- SEQ_ENCLK16_CLK_OUT, /* 22 */
- SEQ_SEL4_16B, /* 23 */
- XTAL_CAPSELECT, /* 24 */
- IF_SEL_DBL, /* 25 */
- RFSYN_R_DIV, /* 26 */
- SEQ_EXTSYNTHCALIF, /* 27 */
- SEQ_EXTDCCAL, /* 28 */
- AGC_EN_RSSI, /* 29 */
- RFA_ENCLKRFAGC, /* 30 */
- RFA_RSSI_REFH, /* 31 */
- RFA_RSSI_REF, /* 32 */
- RFA_RSSI_REFL, /* 33 */
- RFA_FLR, /* 34 */
- RFA_CEIL, /* 35 */
- SEQ_EXTIQFSMPULSE, /* 36 */
- OVERRIDE_1, /* 37 */
- BB_INITSTATE_DLPF_TUNE, /* 38 */
- TG_R_DIV, /* 39 */
- EN_CHP_LIN_B, /* 40 */
-
- /* Channel Change Control Names */
- DN_POLY = 51, /* 51 */
- DN_RFGAIN, /* 52 */
- DN_CAP_RFLPF, /* 53 */
- DN_EN_VHFUHFBAR, /* 54 */
- DN_GAIN_ADJUST, /* 55 */
- DN_IQTNBUF_AMP, /* 56 */
- DN_IQTNGNBFBIAS_BST, /* 57 */
- RFSYN_EN_OUTMUX, /* 58 */
- RFSYN_SEL_VCO_OUT, /* 59 */
- RFSYN_SEL_VCO_HI, /* 60 */
- RFSYN_SEL_DIVM, /* 61 */
- RFSYN_RF_DIV_BIAS, /* 62 */
- DN_SEL_FREQ, /* 63 */
- RFSYN_VCO_BIAS, /* 64 */
- CHCAL_INT_MOD_RF, /* 65 */
- CHCAL_FRAC_MOD_RF, /* 66 */
- RFSYN_LPF_R, /* 67 */
- CHCAL_EN_INT_RF, /* 68 */
- TG_LO_DIVVAL, /* 69 */
- TG_LO_SELVAL, /* 70 */
- TG_DIV_VAL, /* 71 */
- TG_VCO_BIAS, /* 72 */
- SEQ_EXTPOWERUP, /* 73 */
- OVERRIDE_2, /* 74 */
- OVERRIDE_3, /* 75 */
- OVERRIDE_4, /* 76 */
- SEQ_FSM_PULSE, /* 77 */
- GPIO_4B, /* 78 */
- GPIO_3B, /* 79 */
- GPIO_4, /* 80 */
- GPIO_3, /* 81 */
- GPIO_1B, /* 82 */
- DAC_A_ENABLE, /* 83 */
- DAC_B_ENABLE, /* 84 */
- DAC_DIN_A, /* 85 */
- DAC_DIN_B, /* 86 */
-#ifdef _MXL_PRODUCTION
- RFSYN_EN_DIV, /* 87 */
- RFSYN_DIVM, /* 88 */
- DN_BYPASS_AGC_I2C /* 89 */
-#endif
-} MXL5005_ControlName;
-
-/* End of common.h */
-
-/*
- * The following context is source code provided by MaxLinear.
- * MaxLinear source code - Common_MXL.h (?)
- */
-
-void InitTunerControls(Tuner_struct *Tuner);
-u16 MXL_BlockInit(Tuner_struct *Tuner);
-u16 MXL5005_RegisterInit(Tuner_struct *Tuner);
-u16 MXL5005_ControlInit(Tuner_struct *Tuner);
-#ifdef _MXL_INTERNAL
-u16 MXL5005_MXLControlInit(Tuner_struct *Tuner);
-#endif
-
-u16 MXL5005_TunerConfig(Tuner_struct *Tuner,
- u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */
- u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */
- u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */
- u32 IF_out, /* Desired IF Out Frequency */
- u32 Fxtal, /* XTAL Frequency */
- u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */
- u16 TOP, /* 0: Dual AGC; Value: take over point */
- u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */
- u8 CLOCK_OUT, /* 0: turn off clock out; 1: turn on clock out */
- u8 DIV_OUT, /* 4MHz or 16MHz */
- u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */
- u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */
- u8 Mod_Type, /* Modulation Type; */
- /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */
- u8 TF_Type /* Tracking Filter Type */
- /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */
- );
-
-void MXL_SynthIFLO_Calc(Tuner_struct *Tuner);
-void MXL_SynthRFTGLO_Calc(Tuner_struct *Tuner);
-u16 MXL_RegWrite(Tuner_struct *Tuner, u8 RegNum, u8 RegVal);
-u16 MXL_RegRead(Tuner_struct *Tuner, u8 RegNum, u8 *RegVal);
-u16 MXL_ControlWrite(Tuner_struct *Tuner, u16 ControlNum, u32 value);
-u16 MXL_ControlWrite_Group(Tuner_struct *Tuner, u16 ControlNum, u32 value, u16 controlGroup);
-u16 MXL_ControlRead(Tuner_struct *Tuner, u16 ControlNum, u32 * value);
-u16 MXL_ControlRegRead(Tuner_struct *Tuner, u16 ControlNum, u8 *RegNum, int *count);
-void MXL_RegWriteBit(Tuner_struct *Tuner, u8 address, u8 bit, u8 bitVal);
-u16 MXL_IFSynthInit(Tuner_struct * Tuner );
-u16 MXL_TuneRF(Tuner_struct *Tuner, u32 RF_Freq);
-u16 MXL_OverwriteICDefault(Tuner_struct *Tuner);
-u16 MXL_SetGPIO(Tuner_struct *Tuner, u8 GPIO_Num, u8 GPIO_Val);
-u32 MXL_Ceiling(u32 value, u32 resolution);
-u32 MXL_GetXtalInt(u32 Xtal_Freq);
-
-u16 MXL_GetInitRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
-u16 MXL_GetCHRegister(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
-u16 MXL_GetCHRegister_ZeroIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
-u16 MXL_GetCHRegister_LowIF(Tuner_struct *Tuner, u8 * RegNum, u8 *RegVal, int *count);
-u16 MXL_GetMasterControl(u8 *MasterReg, int state);
-
-#ifdef _MXL_PRODUCTION
-u16 MXL_VCORange_Test(Tuner_struct *Tuner, int VCO_Range);
-u16 MXL_Hystersis_Test(Tuner_struct *Tuner, int Hystersis);
-#endif
-
-/* Constants */
-#define MXL5005S_REG_WRITING_TABLE_LEN_MAX 104
-#define MXL5005S_LATCH_BYTE 0xfe
-
-/* Register address, MSB, and LSB */
-#define MXL5005S_BB_IQSWAP_ADDR 59
-#define MXL5005S_BB_IQSWAP_MSB 0
-#define MXL5005S_BB_IQSWAP_LSB 0
-
-#define MXL5005S_BB_DLPF_BANDSEL_ADDR 53
-#define MXL5005S_BB_DLPF_BANDSEL_MSB 4
-#define MXL5005S_BB_DLPF_BANDSEL_LSB 3
-
-/* Standard modes */
-enum
-{
- MXL5005S_STANDARD_DVBT,
- MXL5005S_STANDARD_ATSC,
-};
-#define MXL5005S_STANDARD_MODE_NUM 2
-
-/* Bandwidth modes */
-enum
-{
- MXL5005S_BANDWIDTH_6MHZ = 6000000,
- MXL5005S_BANDWIDTH_7MHZ = 7000000,
- MXL5005S_BANDWIDTH_8MHZ = 8000000,
-};
-#define MXL5005S_BANDWIDTH_MODE_NUM 3
-
-/* Top modes */
-enum
-{
- MXL5005S_TOP_5P5 = 55,
- MXL5005S_TOP_7P2 = 72,
- MXL5005S_TOP_9P2 = 92,
- MXL5005S_TOP_11P0 = 110,
- MXL5005S_TOP_12P9 = 129,
- MXL5005S_TOP_14P7 = 147,
- MXL5005S_TOP_16P8 = 168,
- MXL5005S_TOP_19P4 = 194,
- MXL5005S_TOP_21P2 = 212,
- MXL5005S_TOP_23P2 = 232,
- MXL5005S_TOP_25P2 = 252,
- MXL5005S_TOP_27P1 = 271,
- MXL5005S_TOP_29P2 = 292,
- MXL5005S_TOP_31P7 = 317,
- MXL5005S_TOP_34P9 = 349,
-};
+#ifndef __MXL5005S_H
+#define __MXL5005S_H
-/* IF output load */
-enum
-{
- MXL5005S_IF_OUTPUT_LOAD_200_OHM = 200,
- MXL5005S_IF_OUTPUT_LOAD_300_OHM = 300,
+#include <linux/i2c.h>
+#include "dvb_frontend.h"
+
+struct mxl5005s_config {
+
+ /* 7 bit i2c address */
+ u8 i2c_address;
+
+#define IF_FREQ_4570000HZ 4570000
+#define IF_FREQ_4571429HZ 4571429
+#define IF_FREQ_5380000HZ 5380000
+#define IF_FREQ_36000000HZ 36000000
+#define IF_FREQ_36125000HZ 36125000
+#define IF_FREQ_36166667HZ 36166667
+#define IF_FREQ_44000000HZ 44000000
+ u32 if_freq;
+
+#define CRYSTAL_FREQ_4000000HZ 4000000
+#define CRYSTAL_FREQ_16000000HZ 16000000
+#define CRYSTAL_FREQ_25000000HZ 25000000
+#define CRYSTAL_FREQ_28800000HZ 28800000
+ u32 xtal_freq;
+
+#define MXL_DUAL_AGC 0
+#define MXL_SINGLE_AGC 1
+ u8 agc_mode;
+
+#define MXL_TF_DEFAULT 0
+#define MXL_TF_OFF 1
+#define MXL_TF_C 2
+#define MXL_TF_C_H 3
+#define MXL_TF_D 4
+#define MXL_TF_D_L 5
+#define MXL_TF_E 6
+#define MXL_TF_F 7
+#define MXL_TF_E_2 8
+#define MXL_TF_E_NA 9
+#define MXL_TF_G 10
+ u8 tracking_filter;
+
+#define MXL_RSSI_DISABLE 0
+#define MXL_RSSI_ENABLE 1
+ u8 rssi_enable;
+
+#define MXL_CAP_SEL_DISABLE 0
+#define MXL_CAP_SEL_ENABLE 1
+ u8 cap_select;
+
+#define MXL_DIV_OUT_1 0
+#define MXL_DIV_OUT_4 1
+ u8 div_out;
+
+#define MXL_CLOCK_OUT_DISABLE 0
+#define MXL_CLOCK_OUT_ENABLE 1
+ u8 clock_out;
+
+#define MXL5005S_IF_OUTPUT_LOAD_200_OHM 200
+#define MXL5005S_IF_OUTPUT_LOAD_300_OHM 300
+ u32 output_load;
+
+#define MXL5005S_TOP_5P5 55
+#define MXL5005S_TOP_7P2 72
+#define MXL5005S_TOP_9P2 92
+#define MXL5005S_TOP_11P0 110
+#define MXL5005S_TOP_12P9 129
+#define MXL5005S_TOP_14P7 147
+#define MXL5005S_TOP_16P8 168
+#define MXL5005S_TOP_19P4 194
+#define MXL5005S_TOP_21P2 212
+#define MXL5005S_TOP_23P2 232
+#define MXL5005S_TOP_25P2 252
+#define MXL5005S_TOP_27P1 271
+#define MXL5005S_TOP_29P2 292
+#define MXL5005S_TOP_31P7 317
+#define MXL5005S_TOP_34P9 349
+ u32 top;
+
+#define MXL_ANALOG_MODE 0
+#define MXL_DIGITAL_MODE 1
+ u8 mod_mode;
+
+#define MXL_ZERO_IF 0
+#define MXL_LOW_IF 1
+ u8 if_mode;
+
+ /* Stuff I don't know what to do with */
+ u8 AgcMasterByte;
};
-/* MxL5005S extra module alias */
-typedef struct MXL5005S_EXTRA_MODULE_TAG MXL5005S_EXTRA_MODULE;
-
-/* MxL5005S register setting function pointer */
-typedef int
-(*MXL5005S_FP_SET_REGS_WITH_TABLE)(
- struct dvb_usb_device* dib,
- TUNER_MODULE *pTuner,
- unsigned char *pAddrTable,
- unsigned char *pByteTable,
- int TableLen
- );
-
-
-/* MxL5005S register mask bits setting function pointer */
-typedef int
-(*MXL5005S_FP_SET_REG_MASK_BITS)(
- struct dvb_usb_device* dib,
- TUNER_MODULE *pTuner,
- unsigned char RegAddr,
- unsigned char Msb,
- unsigned char Lsb,
- const unsigned char WritingValue
- );
-
-/* MxL5005S spectrum mode setting function pointer */
-typedef int
-(*MXL5005S_FP_SET_SPECTRUM_MODE)(
- struct dvb_usb_device* dib,
- TUNER_MODULE *pTuner,
- int SpectrumMode
- );
-
-/* MxL5005S bandwidth setting function pointer */
-typedef int
-(*MXL5005S_FP_SET_BANDWIDTH_HZ)(
- struct dvb_usb_device* dib,
- TUNER_MODULE *pTuner,
- unsigned long BandwidthHz
- );
-
-/* MxL5005S extra module */
-struct MXL5005S_EXTRA_MODULE_TAG
-{
- /* MxL5005S function pointers */
- MXL5005S_FP_SET_REGS_WITH_TABLE SetRegsWithTable;
- MXL5005S_FP_SET_REG_MASK_BITS SetRegMaskBits;
- MXL5005S_FP_SET_SPECTRUM_MODE SetSpectrumMode;
- MXL5005S_FP_SET_BANDWIDTH_HZ SetBandwidthHz;
-
- /* MxL5005S extra data */
- unsigned char AgcMasterByte; /* Variable name in MaxLinear source code: AGC_MASTER_BYTE */
-
- /* MaxLinear defined struct */
- Tuner_struct MxlDefinedTunerStructure;
-};
-/* End of common_mxl.h (?) */
+#if defined(CONFIG_MEDIA_TUNER_MXL5005S) || \
+ (defined(CONFIG_MEDIA_TUNER_MXL5005S_MODULE) && defined(MODULE))
+extern struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c,
+ struct mxl5005s_config *config);
+#else
+static inline struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c,
+ struct mxl5005s_config *config)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif /* CONFIG_DVB_TUNER_MXL5005S */
#endif /* __MXL5005S_H */
projects / linux-2.6 / blobdiff