Merge branches 'at91', 'dyntick', 'ep93xx', 'iop', 'ixp', 'misc', 'orion', 'omap...

[linux-2.6] / drivers / char / drm / radeon_cp.c

diff --git a/drivers/char/drm/radeon_cp.c b/drivers/char/drm/radeon_cp.c
index 599187558abbba53585f55839031dc72410f67a0..e53158f0ecb5c9ebf074bbe241df3f60986e0987 100644 (file)
--- a/drivers/char/drm/radeon_cp.c
+++ b/drivers/char/drm/radeon_cp.c
@@ -113,6 +113,30 @@ static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_lo
                RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 }
 
+static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
+{
+       u32 agp_base_hi = upper_32_bits(agp_base);
+       u32 agp_base_lo = agp_base & 0xffffffff;
+
+       if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
+               R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
+               R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
+       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
+               RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
+               RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
+       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
+               R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
+               R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
+       } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480) {
+               RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+               RADEON_WRITE(RS480_AGP_BASE_2, 0);
+       } else {
+               RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
+               if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
+                       RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
+       }
+}
+
 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 {
        drm_radeon_private_t *dev_priv = dev->dev_private;
@@ -180,12 +204,12 @@ static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
                RADEON_WRITE(R300_RB3D_DSTCACHE_CTLSTAT, tmp);
 
                /* 2D */
-               tmp = RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT);
+               tmp = RADEON_READ(R300_DSTCACHE_CTLSTAT);
                tmp |= RADEON_RB3D_DC_FLUSH_ALL;
-               RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
+               RADEON_WRITE(R300_DSTCACHE_CTLSTAT, tmp);
 
                for (i = 0; i < dev_priv->usec_timeout; i++) {
-                       if (!(RADEON_READ(RADEON_RB2D_DSTCACHE_CTLSTAT)
+                       if (!(RADEON_READ(R300_DSTCACHE_CTLSTAT)
                          & RADEON_RB3D_DC_BUSY)) {
                                return 0;
                        }
@@ -542,9 +566,8 @@ static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 
 #if __OS_HAS_AGP
        if (dev_priv->flags & RADEON_IS_AGP) {
-               RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev->agp->base);
-               if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
-                       RADEON_WRITE(RADEON_AGP_BASE_2, 0);
+               radeon_write_agp_base(dev_priv, dev->agp->base);
+
                radeon_write_agp_location(dev_priv,
                             (((dev_priv->gart_vm_start - 1 +
                                dev_priv->gart_size) & 0xffff0000) |
@@ -721,14 +744,7 @@ static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
                IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
                                                      RS480_REQ_TYPE_SNOOP_DIS));
 
-               if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) {
-                       IGP_WRITE_MCIND(RS690_MC_AGP_BASE,
-                                       (unsigned int)dev_priv->gart_vm_start);
-                       IGP_WRITE_MCIND(RS690_MC_AGP_BASE_2, 0);
-               } else {
-                       RADEON_WRITE(RADEON_AGP_BASE, (unsigned int)dev_priv->gart_vm_start);
-                       RADEON_WRITE(RS480_AGP_BASE_2, 0);
-               }
+               radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 
                dev_priv->gart_size = 32*1024*1024;
                temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
@@ -1272,6 +1288,7 @@ static int radeon_do_resume_cp(struct drm_device * dev)
        radeon_cp_init_ring_buffer(dev, dev_priv);
 
        radeon_do_engine_reset(dev);
+       radeon_enable_interrupt(dev);
 
        DRM_DEBUG("radeon_do_resume_cp() complete\n");