drm/radeon: add hier-z registers for r300 and r500 chipsets

[linux-2.6] / drivers / char / drm / r300_cmdbuf.c

diff --git a/drivers/char/drm/r300_cmdbuf.c b/drivers/char/drm/r300_cmdbuf.c
index 329733a48b64d1daee78e8f2c43495e0a0ccfb7e..702df45320f7bcc897439e8b38a1f8d74200c5c4 100644 (file)
--- a/drivers/char/drm/r300_cmdbuf.c
+++ b/drivers/char/drm/r300_cmdbuf.c
@@ -190,7 +190,7 @@ void r300_init_reg_flags(struct drm_device *dev)
        ADD_RANGE(0x42C0, 2);
        ADD_RANGE(R300_RS_CNTL_0, 2);
 
-       ADD_RANGE(0x43A4, 2);
+       ADD_RANGE(R300_SC_HYPERZ, 2);
        ADD_RANGE(0x43E8, 1);
 
        ADD_RANGE(0x46A4, 5);
@@ -209,14 +209,12 @@ void r300_init_reg_flags(struct drm_device *dev)
        ADD_RANGE(0x4E50, 9);
        ADD_RANGE(0x4E88, 1);
        ADD_RANGE(0x4EA0, 2);
-       ADD_RANGE(R300_RB3D_ZSTENCIL_CNTL_0, 3);
-       ADD_RANGE(R300_RB3D_ZSTENCIL_FORMAT, 4);
-       ADD_RANGE_MARK(R300_RB3D_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);    /* check offset */
-       ADD_RANGE(R300_RB3D_DEPTHPITCH, 1);
-       ADD_RANGE(0x4F28, 1);
-       ADD_RANGE(0x4F30, 2);
-       ADD_RANGE(0x4F44, 1);
-       ADD_RANGE(0x4F54, 1);
+       ADD_RANGE(R300_ZB_CNTL, 3);
+       ADD_RANGE(R300_ZB_FORMAT, 4);
+       ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET);      /* check offset */
+       ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
+       ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
+       ADD_RANGE(R300_ZB_ZMASK_OFFSET, 13);
 
        ADD_RANGE(R300_TX_FILTER_0, 16);
        ADD_RANGE(R300_TX_FILTER1_0, 16);
@@ -229,7 +227,7 @@ void r300_init_reg_flags(struct drm_device *dev)
        ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
 
        /* Sporadic registers used as primitives are emitted */
-       ADD_RANGE(R300_RB3D_ZCACHE_CTLSTAT, 1);
+       ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
        ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
        ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
        ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
@@ -243,6 +241,7 @@ void r300_init_reg_flags(struct drm_device *dev)
                ADD_RANGE(R500_RS_INST_0, 16);
                ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
                ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
+               ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
        } else {
                ADD_RANGE(R300_PFS_CNTL_0, 3);
                ADD_RANGE(R300_PFS_NODE_0, 4);
@@ -719,8 +718,9 @@ static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
        BEGIN_RING(6);
        OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
        OUT_RING(R300_RB3D_DSTCACHE_UNKNOWN_0A);
-       OUT_RING(CP_PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
-       OUT_RING(R300_RB3D_ZCACHE_UNKNOWN_03);
+       OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
+       OUT_RING(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE|
+                R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
        OUT_RING(CP_PACKET3(RADEON_CP_NOP, 0));
        OUT_RING(0x0);
        ADVANCE_RING();